An 8-GS/s 200-MHz Bandwidth 68-mW $\Delta\Sigma$ DAC in 65-nm CMOS

Bhide, Ameya; Najari, Omid E.; Mesgarzadeh, Behzad; Alvandpour, Atila

doi:10.1109/tcsii.2013.2258272

Cited by 21 publications

(17 citation statements)

References 9 publications

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“…7 shows the 8 GHz operation of the modulator (1 V supply) and the DAC. The DAC dynamic performance at 8 GHz has been presented in [5]. Beyond 8 GHz, the DAC dynamic performance deteriorates but nevertheless this still allows the checking of modulator operation.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…2) simplifies the final multiplexing and the clock generation but this pushes the logic to operate at a half-rate clock, which is still a challenging task. A ∆Σ DAC that utilizes this strategy was previously presented in [5]. A study of the delays within the integrator is essential for achieving a high speed using only two-channel interleaving and is the main focus of this paper.…”

Section: Introductionmentioning

confidence: 99%

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Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators

Bhide

Alvandpour

2013

2013 Norchip

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Abstract-Implementation of wireless wideband transmitters using ∆Σ DACs requires very high speed modulators. Digital MASH ∆Σ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ∆Σ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ∆Σ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.

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Section: Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators

Bhide

Alvandpour

2013

2013 Norchip

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“…TIDSM DACs have received attention only recently as compared to TIDSM ADCs and very few TIDSM DACs had been reported at the time of the start of this dissertation work [33,34]. Hence, this dissertation aims to further improve the performance of the TIDSM DACs through architectural and circuit level techniques (Papers I & III) [35,36]. The performance limitations of TIDSM DACs are also investigated (Papers II, IV-V) [37][38][39].…”

Section: Organization and Scope Of Dissertationmentioning

confidence: 99%

“…Additionally, a return-to-zero (RZ) DAC may be required for improved dynamic performance [48]. In these cases, the two generated polyphase outputs, y 0 and y 1 are then multiplexed by the same half-rate f s /2 clock to an effective f s sampling rate and then fed to the DAC [35,48]. The final full-rate multiplexing before the DAC is sensitive to both the edges of the f s /2 clock as new data is presented to the DAC on both the edges.…”

Section: Effect Of Clock Duty Cyclementioning

confidence: 99%

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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“…It is hard for conventional digital-to-analog converters to produce ≈10-bit resolution at this high IF. However, the time-interleaved ∆Σ-based DACs [92,93] have the potential to carry out the task. In these architectures, multiple ∆Σ units, clocked at a lower frequency, are time-interleaved.…”

Section: Motivationmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

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An 8-GS/s 200-MHz Bandwidth 68-mW $\Delta\Sigma$ DAC in 65-nm CMOS

Cited by 21 publications

References 9 publications

Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators

Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Complexity and Power Reduction in Digital Delta-Sigma Modulators

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An 8-GS/s 200-MHz Bandwidth 68-mW $\Delta\Sigma$ DAC in 65-nm CMOS

Cited by 21 publications

References 9 publications

Critical path analysis of two-channel interleaved digital MASH &#x0394;&#x03A3; modulators

Critical path analysis of two-channel interleaved digital MASH &#x0394;&#x03A3; modulators

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Complexity and Power Reduction in Digital Delta-Sigma Modulators

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Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators

Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators