An adaptive CFAR embedded system architecture for target detection

Djemal, Ridha; Belwafi, Kais; Alshebeili, Saleh A.

doi:10.1007/s10617-013-9121-6

Cited by 4 publications

(3 citation statements)

References 16 publications

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“…Table 4 shows a comparison of the results between the proposed method and other CFAR processors in [ 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 ]. For a fair comparison, we compared the speed performance in terms of the normalized operation time,

, which was calculated based on FPGA process technology [ 32 ].…”

Section: Hardware Architecturementioning

confidence: 99%

“…An ACOSD CFAR-based algorithm was implemented in [ 22 , 23 , 24 , 25 ] for the case where the background distribution is log-normal. The CFAR processors in [ 22 , 25 ] have low complexity and fast operation time but cannot be applied to various environments, and a proposed method [ 23 ] has a problem with slow operation time. The CFAR processor presented in [ 24 ] has a fast operation time but has high hardware complexity in supporting various algorithms.…”

Section: Hardware Architecturementioning

confidence: 99%

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FPGA Implementation of Efficient CFAR Algorithm for Radar Systems

Sim

Heo

Jung

et al. 2023

Sensors

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The constant false-alarm rate (CFAR) algorithm is essential for detecting targets during radar signal processing. It has been improved to accurately detect targets, especially in nonhomogeneous environments, such as multitarget or clutter edge environments. For example, there are sort-based and variable index-based algorithms. However, these algorithms require large amounts of computation, making them difficult to apply in radar applications that require real-time target detection. We propose a new CFAR algorithm that determines the environment of a received signal through a new decision criterion and applies the optimal CFAR algorithms such as the modified variable index (MVI) and automatic censored cell averaging-based ordered data variability (ACCA-ODV). The Monte Carlo simulation results of the proposed CFAR algorithm showed a high detection probability of 93.8% in homogeneous and nonhomogeneous environments based on an SNR of 25 dB. In addition, this paper presents the hardware design, field-programmable gate array (FPGA)-based implementation, and verification results for the practical application of the proposed algorithm. We reduced the hardware complexity by time-sharing sum and square operations and by replacing division operations with multiplication operations when calculating decision parameters. We also developed a low-complexity and high-speed sorter architecture that performs sorting for the partial data in leading and lagging windows. As a result, the implementation used 8260 LUTs and 3823 registers and took 0.6 μs to operate. Compared with the previously proposed FPGA implementation results, it is confirmed that the complexity and operation speed of the proposed CFAR processor are very suitable for real-time implementation.

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, which was calculated based on FPGA process technology [ 32 ].…”

Section: Hardware Architecturementioning

confidence: 99%

Section: Hardware Architecturementioning

confidence: 99%

FPGA Implementation of Efficient CFAR Algorithm for Radar Systems

Sim

Heo

Jung

et al. 2023

Sensors

View full text Add to dashboard Cite

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“…In [26], the hardware architecture of an energy-CFAR processor was described for adaptive filtering based on energy analysis of radar echoes. [27] reported an FPGA-based CFAR target detector for Log-normal clutter based on forward and backward automatic censored cell algorithms. [28] realized a real-time adaptive OS-CFAR processor for homing application in marine environments using KINTEX-Ultrascale FPGA.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable hardware architecture for Mean Level and log-t CFAR detectors in FPGA implementations

Jiafei

Jiang

Yang

et al. 2019

IEICE Electron. Express

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For radar target detection, the selection of the optimal constant false alarm rate (CFAR) detector usually relies on clutter distribution types. By integrating two types of Mean Level and log-t CFAR detectors, a reconfigurable hardware architecture is proposed and implemented on field programmable gate array (FPGA). It allows to switch a suitable detector for specific clutter distribution and configure the parameters including the number of reference and guard cells, the threshold factor, and the desired false alarm probability. Synthesis results reveal its advantages of occupying 18% less hardware resources than the architecture that naively integrates two types of detectors. According to the experimental results, the proposed architecture can perform a processing speed of 100 MHz and require only 83 microseconds for a clutter of 8192 samples.

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