An Analysis of Single Event Upset Dependencies on High Frequency and Architectural Implementations within Actel RTAX-S Family Field Programmable Gate Arrays

Abstract

In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz.

New Reprogrammable and Non-Volatile Radiation-Tolerant FPGA: RT ProASIC®3

“…The global-error cross-sections are dependent on the clock frequency because they are due to the SET in the IO bank or clock global signals. It is well known that SET induced errors have a strong dependence on the clock frequency [Berg et al, 2006]. For the design D2, only errors type 2 and 3 have been observed, while for D3 only errors type 3 have been observed, which means that each SEE observed on the TMR'd design (D3) always affected an entire IO bank.…”

Experimental Verification of Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems

“…Generally, SERs in real VLSI systems vary depending on the input patterns. This is because the number of sensitive nodes connected to each FF varies depending on the test condition (static or dynamic), as discussed in [8]. Therefore, to evaluate the radiation hardness of the system more precisely, it is necessary to analyze SERs at each FF under the dynamic conditions as well as the static condition.…”

“…to obtain the SERs in the chip, we should design specialized circuits dedicated to obtain soft error parameters, such as the shift register circuits [6]- [8], apart from the main circuits for target applications. From the results obtained by the parameter extraction circuits, we should estimate, not measure, SERs in the main circuits.…”

Risk Reduction for Use of Complex Devices in Space Projects

“…In its simplest form, the upper bound of the design's possible state space is represented as State Space number of DFFs implemented within the DUT [2] (1)…”