An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling

Ok, Sunghwa; Chung, Kee Yun; Koo, Jae-Mean; Kim, Chulwoo

doi:10.1109/tvlsi.2009.2019757

Cited by 23 publications

(15 citation statements)

References 17 publications

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“…Structure of the frequency multipliers in (a) [11], (b) [12], and (c) [13]. suitable for high-frequency multiplied clock generation with low power and a small area.…”

Section: Previous Frequency Multipliersmentioning

confidence: 99%

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High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

Ryu

Jung

et al. 2016

IEEE Trans. VLSI Syst.

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A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive-and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-µm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz-3.3 GHz. The frequency multiplier achieves a power consumption to a frequency ratio of 2.9 µW/MHz. Index Terms-Clock generator, delay-locked loop (DLL), edge combiner, frequency multiplier.

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“…Structure of the frequency multipliers in (a) [11], (b) [12], and (c) [13]. suitable for high-frequency multiplied clock generation with low power and a small area.…”

Section: Previous Frequency Multipliersmentioning

confidence: 99%

“…Fig. 1(b) shows the structure of the frequency multiplier in [12]. This frequency multiplier is composed of a multiplication-ratio control logic, an AND-gate-based pulse generator, and a differential cascade voltage switch (SW) logic (DCVSL)-stage-based edge combiner.…”

Section: Previous Frequency Multipliersmentioning

confidence: 99%

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

Ryu

Jung

et al. 2016

IEEE Trans. VLSI Syst.

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“…This way, the proposed DLL instantly corrects any stuck false locks by resetting the PD. This is compared with other approaches in [3]- [5], [8], and [9], in which the stuck false lock is corrected after the DLL falls into a harmonic-lock condition.…”

Section: B Correcting False Locks With Self-resetmentioning

confidence: 99%

“…In addition, the operations depend on the duty ratio of the reference clock; therefore, a duty correction circuit is also required. The works in [4] and [5] use a simple logic to prevent the false-lock problem but still depend on the duty ratio of the input clock. The DLL used in [6] improved the duty ratio independence and utilized multiphase clocks for an antifalse lock without an external reset signal for the PD.…”

Section: Introductionmentioning

confidence: 99%

“…In particular, the proposed DLL immediately corrects any stuck false locks by resetting the PD internally. This is compared with other approaches in [3]- [5], [8], and [9], in which the stuck false lock is not corrected until the DLL falls into a harmonic-lock condition. In the proposed DLL scheme, the internal and immediate correction process guarantees the correct operation under any abrupt operating condition change such as power on/off, ESD induced noise, or abrupt reference frequency changes, which are common in the display interface environment.…”

Section: Introductionmentioning

confidence: 99%

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A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- $\mu\hbox{m}$ CMOS

Moon

Kong

Ryu

et al. 2014

IEEE Trans. Circuits Syst. II

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This brief describes a wide-range operating falselock-free delay-locked loop (DLL) for a low-voltage differential signaling (LVDS) display interface. A false-lock detector circuit and a self-reset circuit internally prevent any possible false locks in a robust way. The proposed DLL immediately removes stuck false locks caused by an improper phase detector state. The DLL circuit does not require the duty ratio of the input clock to be 50%. The proposed circuit has been fabricated using the 0.15-μm 1P-6M mixed-mode CMOS technology. The proposed DLL is implemented for an LVDS display interface and supports operating from 20 to 135 MHz without any error. It consumes 2.2 mW under a 130-MHz operation.Index Terms-Complementary metal-oxide-semiconductor (CMOS), delay-locked loop (DLL), display interface, false lock, harmonic lock.

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An all‐digital DLL with duty‐cycle correction using reusable TDC

Kao

Hsieh

Cheng

2015

Circuit Theory & Apps

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This paper presents the design of an all-digital delay-locked loop (ADDLL) with duty-cycle correction using reusable time-to-digital converter (TDC). The proposed ADDLL uses a reusable TDC for achieving a wide-operating frequency range. In addition, it achieves the frequency doubling output clock easily by changing the quantization interval. It is implemented in a 0.18-μm complementary metal-oxide semiconductor technology. This circuit corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The output duty cycle is corrected to 50 ± 1.5% as the input duty cycle ranges from 25% to 75%. The acceptable input frequency range is from 300 to 900 MHz without frequency doubling. The acceptable input frequency range is from 150 to 450 MHz when using frequency doubling. It dissipates 6.2 mW from a 1.8-V supply at 900 MHz. The peak-to-peak and RMS jitters at 900 MHz are 14 and 1.8 ps, respectively.

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An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling

Cited by 23 publications

References 17 publications

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- $\mu\hbox{m}$ CMOS

An all‐digital DLL with duty‐cycle correction using reusable TDC

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