An automated shielding algorithm and tool for dynamic circuits

Yee, Gin; Christopherson, R.; Thorp, T.; Wong, Ban P.; Schen, C.

doi:10.1109/isqed.2000.838898

Cited by 6 publications

(3 citation statements)

References 8 publications

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“…Therefore, elimination of the worst-case couplingtransitions can reduce the worst-case delay. A simple method [8] is to insert shield lines (Vdd or Vss) between adjacent wires of the bus. The self-shield encoding scheme [9] is also well suited for elimination of the worst-case crosstalk delay.…”

Section: Introductionmentioning

confidence: 99%

An energy-efficient temporal encoding circuit technique for on-chip high performance buses

Qing-li

Wang

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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In this paper, we propose a novel temporal encoding circuit for generic on-chip buses that enables higher performance while reducing peak energy, average energy and peak current. The proposed circuit dynamically generates shield signals depending on the current and previous state of input data signals to eliminate the worst-case coupling-transitions between adjacent wires. Comparisons to standard on-chip buses of various lengths with optimal repeater insertion in the 0.18-µm CMOS technology show that on-chip buses encoded by such circuit can achieve up to 23% increase in performance, and also provide gains in peak energy (up to 56%) and peak current (up to 60%) at all delay targets. The simulation results of various random input data streams show that the temporally encoded buses obtain up to 44% average energy savings over an optimal standard repeater bus.

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Section: Introductionmentioning

confidence: 99%

An energy-efficient temporal encoding circuit technique for on-chip high performance buses

Qing-li

Wang

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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“…However, the inherent complexity of the associated encoder and decoder structures sharply limits its applicability. Among the techniques that are proposed to handle crosstalk at the design stage is the shielding method [4]. This method is implemented by adding a VDD and VSS "shield" between the data lines.…”

Section: Introductionmentioning

confidence: 99%

A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses

Ayoub

Orailoğlu

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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In this paper we propose a coding scheme for general-purpose applications that can reduce power dissipation, crosstalk noise and crosstalk delay on the bus lines while simultaneously detecting errors at run time. The reduction in power dissipation can be achieved through reducing the bus switching activity. Not only is the switching activity in individual lines reduced but so is the coupling activity across the adjacent lines, the major contributor to the overall power dissipation in deep submicron technology. Detailed analysis of crosstalk noise and delay shows that eliminating certain patterns of transitions and reducing the infeasible ones in terms of crosstalk noise and power dissipation is a feasible strategy for alleviating these problems. We propose an encoding technique consisting of the use of predefined patterns of transitions, one for each possible combination of input data, to generate the codewords. The restriction to the predefined patterns of transitions enables fast encoding and low hardware overhead. This work presents an extensive analysis of the consequent reduction in crosstalk and power. SPICE derived experimental results show a reduction in worst case crosstalk delay and noise, ranging up to 24% and 10% respectively. Extensive experimental results for various applications show significant reduction in power dissipation ranging up to 44% for switching activity on the bus lines and up to 25% for coupling activity. The results also show a drastic reduction ranging up to 98% in the number of patterns that are most likely to produce crosstalk errors.

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“…A common method of shielding is placing ground or power lines at the sides of a victim signal line to reduce noise and delay uncertainty [5]. Although shielding is commonly used [6], [7], a peak noise model for shielded interconnects model. The effects of the shield width, length, separation between the shield and the signal, and the number of connections tieing the shield to ground on the crosstalk noise are investigated.…”

Section: Introductionmentioning

confidence: 99%

Effect of shield insertion on reducing crosstalk noise between coupled interconnects

Zhang

Friedman

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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Abstract-Placing shields around a victim signal line is a common way to enhance signal integrity while minimizing delay uncertainty. For two coupled interconnects with a shield between the lines, the coupling noise can produce a peak noise of 15% ofmodel is used to develop an analytic estimate of the peak noise for shielded interconnects. The peak noise model is accurate within an average error of 4.4% as compared to SPICE. The effects of the shield width, length, separation between the shield and the signal, and the number of connections tieing the shield to ground on the overall crosstalk noise are described in this paper. Based on the peak noise model, a minimum number of ground connections for a target shield line with noise constraints is obtained. Inserting a shield line between two coupled interconnects is shown to be more effective in reducing crosstalk noise than increasing the physical separation.

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An automated shielding algorithm and tool for dynamic circuits

Cited by 6 publications

References 8 publications

An energy-efficient temporal encoding circuit technique for on-chip high performance buses

An energy-efficient temporal encoding circuit technique for on-chip high performance buses

A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses

Effect of shield insertion on reducing crosstalk noise between coupled interconnects

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