An efficient algorithm for low power pass transistor logic synthesis

Abstract

In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power reduction in PTL circuits to that of BDD decomposition and solve the latter using the max-flow min-cut technique. We use transistor level power estimates to guide the BDD decomposition algorithm. We present the results obtained by running our algorithm on a set of MCNC benchmark circuits, and show on an average of 47% power reduction over these circuits; the comparison with the previously proposed low power pass transistor logic synthesis algorithms shows an average improvement of over 23% over the best previously published approach.

BDD decomposition for delay oriented pass transistor logic synthesis

“…In our algorithm, we perform this bipartitioning to aim for the minimum area penalty. This approach differs from that of [22] in the objective as well as the application of bipartitioning: aim of that work is power minimization in the combinational logic blocks implemented in PTL, where bipartitioning is applied only once to a given BDD, as opposed to this work which targets delays, and applies bipartitioning recursively.…”

Exact lower bound for the number of switches in series to implement a combinational logic cell

“…5. This way, the use of the lower bound will produce a cell that has smaller pull-up and pull-down networks than PTL [1][2][3][4][5][6][7][8]. Based on example 2, it is possible to see that the NCSP we propose may be used to reduce the length of pull-up and pull-down chains when implementing cell level networks.…”

“…The Pass Transistor Logic (PTL) [1][2][3][4][5][6][7][8] realization of the cell from example 2 would be a 4-4 cell, independently of the BDD variable order used to generate the PTL network [14]. One possible PTL network is shown in Fig.…”

“…The main switch topologies used to design transistor networks for logic cells are Pass Transistor Logic (PTL) [1][2][3][4][5][6][7][8] and Complementary Series/Parallel (CSP) CMOS Logic [9][10][11][12]. PTL topology is composed of a single non-disjoint pull-up/down plane, while CSP topology has two disjoint switch planes: one pull-up plane and one pull-down plane.…”

“…Indeed, the approaches in [1][2][3][4][5][6][7][8] are based on BDDs. Therefore, when discussing PTL networks, we will concentrate our discussion on PTL networks derived from BDDs.…”