An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctuation

This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTLdesign and early floorplanning are performed. In this stage, logic contents are not known, but global structure of power/ground and clock networks, function partitioning and early floorplan give reasonable accuracy for global optimization of the chip. A case study shows the power voltage drop and critical path delay slowdown due to dynamic power voltage drop for a mixed analog-digital chip, and a good match with actual measurements is achieved.

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A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design

Iwabuchi

Sakamoto

Sekine

et al. 1999

Proceedings of the 1999 International Symposium on Physical Design

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An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctuation

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References 4 publications

A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design

A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design

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