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A new circuit recognition and reduction method to extract subcircuit data corresponding to the critical paths, including all relevant parasitics and intemal loading, is presented. Circuit elements extracted from layout pattem data are combined together to reconstruct logic gates, and a structure of the gates are recognized by the connection between the gate terminals. The recognized circuit data is reduced by tracing signal flows and picking up the gates along the specified critical paths. The circuit elements connected between a remaining net and an eliminated net are terminated as capacitive loads, and parasitic elements are merged or eliminated when the estimated error is permissible, compared with the specified error tolerance. The error is estimated by the first-order moment of the impulse response. Results on logic macrocells and memory peripheral control circuits show that the reduced circuit sizes are 15 -50 times smaller, resulting in circuit simulation speedups of 50x -300x.

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A highly accurate one‐dimensional table model has been developed for an MOS transistor simulation used in a circuit simulation necessary for the VLSI design. The usefulness of the model for the circuit simulation has been tested. Traditionally, the one‐dimensional table model has been used in the area where high precision is not required, such as the timing simulators. It is not sufficient for simulation of a high‐precision circuit and the accuracy has been a particular problem for the MOS transistor of submicron level. In the new one‐dimensional table model, the two‐dimensional effect of the drain and gate electric fields is included and only two one‐dimensional tables are added. The model can be applied to a high‐precision circuit simulation. This model has been applied to three devices with the effective channel length of 0.66 ∼ 2.30 μm fabricated in different processes. It was found that the maximum of the average relative error within the practical voltage range is 3.87% which corresponds to the acuracy four times that in the conventional model. Increase of the error for the variation of the substrate voltage is especially small. It has been demonstrated that the present one‐dimensional table model is a transistor model capable of high‐precision circuit simulation.