An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

Abstract

In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p 2 ), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations are carried out to analyse the performance of the FRIT core developed.

Efficient reconfigurable architectures for 3D medical image compression

“…As an example, the wavelet transform has been extensively used as a solution to the problem of the short time Fourier transform (STFT), and excels in isolation discontinuities and spikes [71]. However, the wavelet suffers from inflexible directionality, as it does not isolate the smoothness along edges.…”

“…However, the wavelet suffers from inflexible directionality, as it does not isolate the smoothness along edges. This demerit of wavelet is well addressed by the ridgelet and curvelet transforms, as they extend the functionality of wavelets to higher dimensional singularities, and it is proven as an effective tool to perform sparse directional analysis [71]. The basic building block of these transforms is the FRAT.…”

“…An orthonormal, digital and fully invertible form of ridgelets, called the finite ridgelet transform (FRIT) [71], [72] and the FRIT allows superior compaction over wavelets as a result of its directional nature. Therefore, better performance can be achieved in image compression and de-noising applications [71].…”

“…Therefore, better performance can be achieved in image compression and de-noising applications [71].…”

“…In addition to the summary of existing FRAT implementation on FPGA that have been discussed [71][72][73], [75], [76], Table 2.4 lists the important issues, such as the FPGA devices involved, programming approaches as well as the target applications. Virtex-E Handel-C and CoreGen Image processing [72] Virtex-II Handel-C Image processing [73] Virtex-E N/S Image processing [75] Virtex-II Verilog Image processing [76] Virtex-E Handel-C Image processing Note: N/S: Not stated…”