An Energy and Performance Exploration of Network-on-Chip Architectures

Abstract

Abstract-In this paper, we explore the designs of a circuit-switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately evaluate the energy-performance tradeoffs they offer. Power results from the designs placed and routed in a 90-nm CMOS process show that all the architectures dissipate significant idle state power. The additional energy required to route a packet through the router is then shown to be dominated by the data path. This leads to the key result that, if this trend continues, the use of more elaborate control can be justified and will not be immediately limited by the energy budget. A performance analysis also shows that dynamic resource allocation leads to the lowest network latencies, while static allocation may be used to meet QoS goals. Combining the power and performance figures then allows an energy-latency product to be calculated to judge the efficiency of each of the networks. The speculative virtual channel router was shown to have a very similar efficiency to the wormhole router, while providing a better performance, supporting its use for general purpose designs. Finally, area metrics are also presented to allow a comparison of implementation costs.

Proximity coherence for chip multiprocessors

“…As a consequence, schemes that reduce network hop traversals are becoming increasingly attractive. Additionally, advanced on-chip router energy consumption is now comparable to an L1 cache access [4,14,21]. Importantly, this validates the use of the additional L1 cache accesses generated by Proximity Coherence to reduce network utilization.…”

“…First, we assume that network energy consumed is proportional to the amount of data transferred. Work by Banerjee et al [4] shows that, with effective clock-gating, this is the case. In Proximity Coherence, data messages are approximately nine times larger than control messages.…”

“…In our system, we assume a global network that delivers data and control messages with the same latency. Additionally, our work models state of the art router latencies [4]. As detailed in Hossain's work, using such a low latency network reduces the benefits gained through their scheme.…”

Performance Analysis of Shared Buffer Router Architecture for Low Power Applications

“…8, it is clearly shows that the proposed method consumes less power than the conventional methods stated in Table 5. The power consumption of the proposed methodology and conventional methodology ( [10][11][12][13][14][15]) are measured using Xilinx Project Navigator 12.1(power prime) tool.…”

A TDM NoC supporting QoS, multicast, and fast connection set-up

“…One disadvantage of Nostrum is that routing paths, and consequently multicast node sets, must be decided at design time. 2 The paper only mentions that routes are decided at run-time, possibly they are stored in a distributed fashion inside the routers 3 Guaranteed connections have preallocated VCs and setup is assumed to always succeed 4 No explicit connection setup is required, containers can be added and removed at will at runtime by any of the nodes on the route but lack of conflicts must be ensured 5 The distributed version of AEthereal could in theory support multicast at network level, although a solution for configuring the nework for this scenario was not proposed; multicast was proposed using separate connections for each target…”