An Exact Breadth-First Search Algorithm for the Multiple Constant Multiplications Problem

Aksoy, Levent; Güneş, Ece Olcay; Flores, Paulo

doi:10.1109/norchp.2008.4738280

Cited by 32 publications

(54 citation statements)

References 13 publications

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“…Breadth-first search [23] and depth-first search [17] algorithms were proposed by Aksoy et al to optimally solve the MCM problem in a graph-based way. The depth-first search is able to solve MCM instances in a reasonable time but cannot handle different constraints or cost metrics.…”

Section: Using Additions Subtractions and Bit Shiftsmentioning

confidence: 99%

FIR filter optimization for video processing on FPGAs

Kumm

Fanghänel

Möller

et al. 2013

EURASIP J. Adv. Signal Process.

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Two-dimensional finite impulse response (FIR) filters are an important component in many image and video processing systems. The processing of complex video applications in real time requires high computational power, which can be provided using field programmable gate arrays (FPGAs) due to their inherent parallelism. The most resource-intensive components in computing FIR filters are the multiplications of the folding operation. This work proposes two optimization techniques for high-speed implementations of the required multiplications with the least possible number of FPGA components. Both methods use integer linear programming formulations which can be optimally solved by standard solvers. In the first method, a formulation for the pipelined multiple constant multiplication problem is presented. In the second method, also multiplication structures based on look-up tables are taken into account. Due to the low coefficient word size in video processing filters of typically 8 to 12 bits, an optimal solution is found for most of the filters in the benchmark used. A complexity reduction of 8.5% for a Xilinx Virtex 6 FPGA could be achieved compared to state-of-the-art heuristics.

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Section: Using Additions Subtractions and Bit Shiftsmentioning

confidence: 99%

FIR filter optimization for video processing on FPGAs

Kumm

Fanghänel

Möller

et al. 2013

EURASIP J. Adv. Signal Process.

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“…The approach presented in [13] provides a very good estimate of the number of additions required in multiple constant multiplication (MCM) designs, is based on heuristic methods involving the performance of exhaustive simulations on a large number of samples. Although some of the CSE algorithms described in section 1 require fewer adders than the CSEBitSlice technique, no concrete method for estimation of the overhead associated with the search and elimination process has been provided.…”

Section: Y(n)mentioning

confidence: 99%

“…Multipliers are the main building blocks in many DSP circuits and are the key factor in determining circuit performance. Most optimization techniques that aim at complexity reduction of DSP circuits rely on the fact that one of the multiplier operands is a constant [1][2][3][4][5][6][7][8][9][10][11][12][13]. However, DSP circuits in reconfigurable systems require generic multipliers as both the multiplier and multiplicand can be variables.…”

Section: Introductionmentioning

confidence: 99%

“…Many optimization techniques proposed for generic multiplier design such as the Radix-4 Booth, Carry Save Array (CSA), and Residue Number Arithmetic (RNA) have been widely published in the literature [14][15][16][17][18][19][20][21]. On the other hand, the application of the common sub-expression elimination technique has also been reported for constant multiplication circuits [1,3,5,[8][9][10][11][12][13]. The CSE optimization technique depends on an exhaustive search process to identify common patterns among the data bits representing the multiplier operand so that the partial products related to these patterns only have to be evaluated once.…”

Section: Introductionmentioning

confidence: 99%

“…For vector or matrix multiplication, significant hardware reduction can be achieved using the CSE optimization technique. In fact, simulation results presented in [1,3,5,13] show that considerable logic resources can be saved using the CSE technique for FIR filter, DFT, and DCT circuit implementations. The CSE techniques for vector and matrix multiplication in the above referenced papers involve multiplication operations in which one of the operands is a constant.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

Szwarc

Kwaśniewski

2010

J Sign Process Syst

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A design technique based on a combination of Common Sub-Expression Elimination and Bit-Slice (CSEBitSlice) arithmetic for hardware and performance optimization of multiplier designs with variable operands is presented in this paper. The CSE-BitSlice technique can be extended to hardware optimization of multiplier circuits operating on vectors or matrices of variables. The CSEBitSlice technique has been applied to the design and implementation of 12×12 and 42×42 bit real multipliers, a complex multiplier, a 6-tap FIR filter, and a 5-point DFT circuit. For comparison purposes, circuit implementations of the same arithmetic and DSP functions have been carried out using Radix-4 Booth and CSA algorithms. Simulation results based on implementations using the Xilinx FPGA 5VLX330FF1760-2 device shows that the circuits based on the CSE-BitSlice techniques require fewer logic resources and yield higher throughput as compared to the CSA and Radix-4 Booth based circuits.

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Multiplication by Constants

de Dinechin,

Kumm

2023

Application-Specific Arithmetic

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An Exact Breadth-First Search Algorithm for the Multiple Constant Multiplications Problem

Cited by 32 publications

References 13 publications

FIR filter optimization for video processing on FPGAs

FIR filter optimization for video processing on FPGAs

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

Multiplication by Constants

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