An experimental fault-tolerant active substrate MPC MCM using standard gate array technology

Seventh IEEE International Conference on Wafer Scale Integration

“…In particular, it can be used to bypass interconnect bus defects in MCM active substrates which are also being investigated for ASP module fabrication [23].…”

“…At such level it is possible to apply methodologies for the management of the clock signals [23], '[24], exploiting the effectiveness of the approaches defined, also fulfilling the design rules of the given industrial site. Therefore, in the Partial Scan definition phase it is not necessary to take into account clock skew problems, since they will be solved globally in the physical design phase.…”

Defect and fault tolerant interconnection strategies for WASP devices

“…Thus, all the six SMN variants have been employed in modeling the routing of a 32-bit WASP bus from the external pads to the ASP core. For brevity, the detailed switch connectivity matrices involved is not shown here but may be found in [23]. Table I1 summarizes the number of bus bitlines (i.e., 32+redundant bitlines) used in all the SMN variants as a consequence of this modeling.…”