2017
DOI: 10.1109/tcsii.2016.2568181
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An Integrated Dual Entropy Core True Random Number Generator

Abstract: In this work, we present the first integrated circuit implementation of our previously proposed dual entropy core TRNG architecture, which is designed following a novel parameter variation-aware approach. A prototype integrated circuit has been fabricated in 180nm CMOS technology. Prototype chip achieved 35Mbps throughput with approximately 33pJ/bit energy efficiency. Random numbers acquired from the prototype chip have successfully passed all NIST 800.22 statistical tests without requiring any post-processing. Show more

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Cited by 29 publications
(10 citation statements)
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“…Field programmable gate array-based applications provide high-speed implementation and reconfigurable design process. In cryptographic applications, FPGAs occupy an important place [28][29][30][31][32][33][34][35]. The proposed design in the third scenario is run on Virtex II Pro XC2VP30 FPGA development board by using Verilog HDL as the source type.…”
Section: Field Programmable Gate Array Implementation Of Chaotic Cellmentioning
confidence: 99%
“…Field programmable gate array-based applications provide high-speed implementation and reconfigurable design process. In cryptographic applications, FPGAs occupy an important place [28][29][30][31][32][33][34][35]. The proposed design in the third scenario is run on Virtex II Pro XC2VP30 FPGA development board by using Verilog HDL as the source type.…”
Section: Field Programmable Gate Array Implementation Of Chaotic Cellmentioning
confidence: 99%
“…Nevertheless, the statistical characteristics of the sequence generated by these systems are highly sensitive to the chaotic system parameters perturbations, causing an issue that must be carefully taken into account when designing the hardware implementation of these TRNGs [96,97,103,[122][123][124][125]. In Figure 12, a CMOS circuit to implement the algebraic calculation of the Sawtooth nonlinear function shown in Figure 11(a) is reported, using cascode current mirrors [111]. In Figure 12, a CMOS circuit to implement the algebraic calculation of the Sawtooth nonlinear function shown in Figure 11(a) is reported, using cascode current mirrors [111].…”
Section: Chaotic Circuitsmentioning
confidence: 99%
“…The electronic design of piecewise linear chaotic maps has been investigated following different approaches and targeting different applications, including true random numbers generation, secure communication, and colored noise generation [96, 104-111, 120, 121]. The complete iterated execution of the computation I n+1 = f (I n ) is obtained by means of a delay block realized with track-and-hold switchedcurrent stages [111,126]. The circuit calculates f (I n ), being the chaotic state variable represented by a current.…”
Section: Chaotic Circuitsmentioning
confidence: 99%
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