An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits

Chatterjee, A.; Nandakumar, M.; Chen, Ih-Chin

doi:10.1109/lpe.1996.547497

Cited by 25 publications

(17 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The power ratio dependency on supply voltage is eliminated, when taking into account the voltage dependency of β and R 0 (supporting the results in [7,8]). …”

Section: Short Circuit Power Dependency On V Tsupporting

confidence: 84%

“…The downsizing of transistors contributes to SC reduction, but is an integral part of most of the existing optimization techniques, both for leakage and for dynamic power. Similarly, the voltage scaling can be effective for overall power reduction and will reduce the absolute values of the SC power, but is not effective for reduction of P SC /P dyn ratio, as was shown in [7,10]. The approach of slope-balancing proves to be effective for SC power reduction [11].…”

Section: Vinmentioning

confidence: 98%

“…However, the portion of the SC power out of the dynamic power can be significant. While in some cases it is assumed to be around 10% of the dynamic power [6], the high dependency of the SC power on slopes may cause an increase of SC to tens of percents out of dynamic power [7].…”

Section: Vinmentioning

confidence: 99%

“…Other researches propose estimation of P SC /P dyn ratio based on empirical simulations [9]. The research in [7] shows the dependency of the SC on the process parameters as part of technology scaling, without addressing MTCMOS processes.…”

Section: Vinmentioning

confidence: 99%

“…In [7] the SC reduction was addressed with regards to technology scaling, while showing the dependency of SC on the threshold voltage of the process. However, in this work the SC reduction is achieved by similar measures as leakage reduction, and becomes significant only for high frequencies.…”

Section: Vinmentioning

confidence: 99%

See 4 more Smart Citations

Short-Circuit Power Reduction by Using High-Threshold Transistors

Morgenshtein

2012

JLPEA

View full text Add to dashboard Cite

Abstract:In this brief paper, the dependency of short-circuit power on threshold voltage is analyzed and utilized for short circuit (SC) power reduction in multi-threshold (MTCMOS) processes. Analytical expressions are developed for estimation of the change of ratio between short-circuit power and dynamic power (P SC /P dyn ) while changing the design process. The analysis shows that the P SC /P dyn ratio can increase significantly if the V T /V dd ratio in new process decreases. An analytical expression is also derived for estimation of potential SC power reduction in MTCMOS processes by replacing low-V T transistors by high-V T devices in the same process. The proposed technique allows significant reduction of SC power without the need for process shift. The simulation results show good correlation with the analytical estimation at cell level, while demonstrating an average SC power saving of 36%. The performance impact is also validated, showing that timing degradation is minor and controllable. The proposed optimization technique is applicable to any multi-threshold process. The technique is simple for implementation, and can be easily integrated in the existing optimization tools.

show abstract

“…The power ratio dependency on supply voltage is eliminated, when taking into account the voltage dependency of β and R 0 (supporting the results in [7,8]). …”

Section: Short Circuit Power Dependency On V Tsupporting

confidence: 84%

Section: Vinmentioning

confidence: 98%

Section: Vinmentioning

confidence: 99%

Section: Vinmentioning

confidence: 99%

Section: Vinmentioning

confidence: 99%

See 3 more Smart Citations

Short-Circuit Power Reduction by Using High-Threshold Transistors

Morgenshtein

2012

JLPEA

View full text Add to dashboard Cite

show abstract

Finding Peak Performance in a Process

Chinnery

Keutzer

Closing the Gap Between ASIC &Amp; Custom

View full text Add to dashboard Cite

Energy Management Techniques for SOC Design

Yasuura

Ishihara

Muroyama

Essential Issues in SOC Design

View full text Add to dashboard Cite

One of the biggest problems in complicated and high-performance SoC design is management of energy and/or power consumption. In this chapter, we present energy management techniques in system design including HW and SW, SoC architecture and logic design. Dynamic power consumption is the major factor of energy consumption in the current CMOS digital circuits. The dynamic power consumption is affected by supply voltage, load capacitance and switching activity. We present approaches to controlling supply voltage, load capacitance and switching activity dynamically and statically in system architecture and algorithm design levels. We also discuss on the memory architecture for reducing power and energy in HW and SW co-design of SoC. In the future CMOS technology, leakage power consumption becomes dominant, because the threshold voltages are scaled as the transistor size shrinks. We summarize the techniques for reducing leakage power in system architecture design. The contents of the chapter include the following issues;(1) power and energy consumptions in SoC design, (2) tradeoff between energy and performance, (3) tradeoff among energy, QoS (i.e., latency and computational precision), reliability, and flexibility (4) techniques for reducing dynamic power consumption, and (5) leakage power reduction techniques.

show abstract

An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits

Cited by 25 publications

References 4 publications

Short-Circuit Power Reduction by Using High-Threshold Transistors

Short-Circuit Power Reduction by Using High-Threshold Transistors

Finding Peak Performance in a Process

Energy Management Techniques for SOC Design

Contact Info

Product

Resources

About