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In this paper the eects of technology scaling on the fraction of active p o w er P a wasted as short-circuit power P s are studied through SPICE simulations. The accuracy of SPICE is veried against experimental data. SPICE simulations show that lowering V T below 0.1V can increase P s =P a signicantly beyond what is expected from increased subthreshold leakage. P s =P a is typically higher at higher V cc but to rst order P s =P a is determined by signal slew rates and V T . It is shown that the input slew rate is constrained by P s =P a at low V T and by performance at higher V T . We show that P s increases with increasing gate sheet resistance. A simple analytical model for this eect is veried against the experimental data and used to determine the gate sheet requirements to maintain Ps/Pa < 10% for sub-0.25m technologies.

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