An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures

Korinth, Jens; Chevallerie, David de la; Koch, Andreas

doi:10.1109/fccm.2015.22

Cited by 22 publications

(10 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this research, we explore a horizontal collaborative solution. Similar work to ours is done in [13] that presents a tool to automatically compose multiple heterogeneous accelerator cores into a unified hardware thread pool. In comparison, our approach includes host CPU for task execution too and relies on commercially available tools to abstract drivers and run-time creation and focuses on performance enhancements and scheduling.…”

Section: Background and Related Workmentioning

confidence: 92%

Simultaneous multiprocessing in a software-defined heterogeneous FPGA

et al. 2018

View full text Add to dashboard Cite

Heterogeneous chips that combine CPUs and FPGAs can distribute processing so that the algorithm tasks are mapped onto the most suitable processing element. New software-defined high-level design environments for these chips use general purpose languages such as C++ and OpenCL for hardware and interface generation without the need for register transfer language expertise. These advances in hardware compilers have resulted in significant increases in FPGA design productivity. In this paper, we investigate how to enhance an existing software-defined framework B Sam Amiri with the FPGA hardware accelerators. Instead of selecting the best processing element for a task and simply offloading onto it, we introduce two schedulers, Dynamic and LogFit, which distribute the tasks among all the resources in an optimal manner. A new platform is created based on interrupts that removes spin-locks and allows the processing cores to sleep when not performing useful work. For a compute-intensive application, we obtained up to 45.56% more throughput and 17.89% less energy consumption when all devices of a Zynq-7000 SoC collaborate in the computation compared against FPGA-only execution.

show abstract

Section: Background and Related Workmentioning

confidence: 92%

Simultaneous multiprocessing in a software-defined heterogeneous FPGA

et al. 2018

View full text Add to dashboard Cite

show abstract

“…When moving from a standard shared memory multi-core architecture to a high speed cluster, the data parallel pattern may be automatically refactored out of the pattern expression modelling application parallelism 3 or individual computations of different, consecutive filter stages may be merged into a single, coarser grain stage 4 to enhance grain and therefore increase application efficiency. Similar reasoning can also be applied to various hardware accelerators, including GP-GPUs and FPGAs [40,46] and, potentially, enable a performance continuum into more distributed systems such as clouds [8]. It is worth pointing out that, provided the set of valid refactoring rules, the policies and the heuristics are suitably tagged with models qualitatively describing their effect w.r.t.…”

Section: Strengths and Weaknesses Of Structured Parallel Programmingmentioning

confidence: 98%

Algorithmic Skeletons and Parallel Design Patterns in Mainstream Parallel Programming

Danelutto

Mencagli

Torquati

et al. 2020

Int J Parallel Prog

View full text Add to dashboard Cite

This paper discusses the impact of structured parallel programming methodologies in state-of-the-art industrial and research parallel programming frameworks. We first recap the main ideas underpinning structured parallel programming models and then present the concepts of algorithmic skeletons and parallel design patterns. We then discuss how such concepts have permeated the wider parallel programming community. Finally, we give our personal overview—as researchers active for more than two decades in the parallel programming models and frameworks area—of the process that led to the adoption of these concepts in state-of-the-art industrial and research parallel programming frameworks, and the perspectives they open in relation to the exploitation of forthcoming massively-parallel (both general and special-purpose) architectures.

show abstract

“…This problem is precisely what motivated the work on ThreadPoolComposer [42], the authors' first effort in this area. TaPaSCo is based on ThreadPoolComposer, which is in turn is closely related to previous work on ReconOS [47], hthreads [54], and FUSE [36].…”

Section: Earlier Workmentioning

confidence: 99%

The TaPaSCo Open-Source Toolflow

Heinz

Hofmann

Korinth

et al. 2021

J Sign Process Syst

Self Cite

View full text Add to dashboard Cite

The integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.

show abstract

An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures

Cited by 22 publications

References 12 publications

Simultaneous multiprocessing in a software-defined heterogeneous FPGA

Simultaneous multiprocessing in a software-defined heterogeneous FPGA

Algorithmic Skeletons and Parallel Design Patterns in Mainstream Parallel Programming

The TaPaSCo Open-Source Toolflow

Contact Info

Product

Resources

About