An ultra‐low power and low jitter frequency synthesizer for 5G wireless communication and IoE applications

Abstract

This paper presents a fully integrated analog phase‐locked loop (PLL) fractional‐N frequency synthesizer for 5G wireless communication and Internet‐of‐Everything (IoE) applications. To demonstrate the effectiveness of this frequency synthesizer, we apply it to three wireless communication standards. Contrary to using Verilog or VHDL to implement the programmable frequency divider, we propose a new approach in the transistor level with a new divide‐by‐2/3 circuit, dynamic asynchronous resettable D and JK flip‐flops, and the OR & AND gates to customize the divider for low‐power, low‐jitter, and fast‐lock time applications. In addition, we have designed a new frequency phase detector (PFD) to overcome the dead region issue. An ultra‐low phase noise and low‐power voltage control oscillator (VCO) is exploited from our previous work with the flicker noise corner frequency around 10 kHz to achieve the lowest possible phase noise. The implementation is done in 180‐nm standard CMOS technology. It covers two frequency ranges including 2.4 to 2.48 GHz and 5 to 5.825 GHz for these wireless communication standards. According to simulations in the worst case, the lock time, rms‐jitter, in‐band fractional spur, power consumption, and jitter‐power figure‐of‐merit of the frequency synthesizer is 18 μs, 56 fs, −63 dBc, 4 mW, and −259, respectively.

A low jitter sub‐sampling phase‐locked loop with sampling thermal noise cancellation technique

“…Phase‐locked loops (PLLs) are widely employed in modern wireline and wireless communication system as frequency synthesis, 1,2 modulation, 3 clock recovery, 4,5 and so forth. With the development of communication technology, the new communication protocols impose more strict requirements on jitter of PLLs.…”