Analog neural network design for RF built-in self-test

Maliuk, Dzmitry; Stratigopoulos, Haralampos-G.; He, Hongyu; Makris, Yiorgos

doi:10.1109/test.2010.5699272

Cited by 27 publications

(15 citation statements)

References 27 publications

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“…The results of synapse multiplication are summed and fed to the corresponding neuron, which performs a squashing function and produces an output either to the next layer or the primary output. The architecture is very modular and can easily be expanded to any number of neurons and inputs within the available silicon area [11].…”

Section: On-chip Classifiermentioning

confidence: 99%

Post-deployment trust evaluation in wireless cryptographic ICs

Jin¹,

Maliuk²,

Makris³

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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The use of side-channel parametric measurements along with statistical analysis methods for detecting hardware Trojans in fabricated integrated circuits has been studied extensively in recent years, initially for digital designs but recently also for their analog/RF counterparts. Such post-fabrication trust evaluation methods, however, are unable to detect dormant hardware Trojans which are activated after a circuit is deployed in its field of operation. For the latter, an on-chip trust evaluation method is required. To this end, we present a general architecture for post-deployment trust evaluation based on on-chip classifiers. Specifically, we discuss the design of an on-chip analog neural network which can be trained to distinguish trusted from untrusted circuit functionality based on simple measurements obtained via on-chip measurement acquisition sensors. The proposed method is demonstrated using a Trojan-free and two Trojan infested variants of a wireless cryptographic IC design, as well as a fabricated programmable neural network experimentation chip. As corroborated by the obtained experimental results, two current measurements suffice for the on-chip classifier to effectively assess trustworthiness and, thereby, detect hardware Trojans that are activated after chip deployment.

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Section: On-chip Classifiermentioning

confidence: 99%

Post-deployment trust evaluation in wireless cryptographic ICs

Jin¹,

Maliuk²,

Makris³

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…While the "inverse" problem of applying machine learning for solving test-related tasks is extensively studied [14], a few papers have been published recently on testing of hardware neural networks. In [15], a neuromorphic BIST architecture was proposed for analog ICs that has as its central block an on-chip neural network that can classify simple measurements directly to 1-bit pass or fail test decisions. However, the test of the neuromorphic BIST wrapper was not studied.…”

Section: Introductionmentioning

confidence: 99%

Self-Testing Analog Spiking Neuron Circuit

El-Sayed¹,

Camuñas-Mesa

Linares-Barranco

et al. 2019

2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (

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Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology.

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“…In this paper, a JTAG protection scheme using statistical learning in chip (SLIC-J) is proposed to monitor user behavior and detect illegitimate access to the JTAG, ultimately protecting user-defined backdoors from being attacked [22], [23]. A similar idea was also proposed in [24]- [26], where an on-chip, neural-network classifier is employed for detecting Trojans in real time. SLIC-J is based on the fact that illegitimate users are prone to behave differently than legitimate users because they are not aware of which JTAG functions are implemented and how they should be operated.…”

Section: Introductionmentioning

confidence: 99%

Detection of Illegitimate Access to JTAG via Statistical Learning in Chip

Ren¹,

Tavares²,

Blanton³

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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IEEE 1149.1, commonly known as the joint test action group (JTAG), is the standard for the test access port and the boundary-scan architecture. The JTAG is primarily utilized at the time of the integrated circuit (IC) manufacture but also in the field, giving access to internal subsystems of the IC, or for failure analysis and debugging. Because the JTAG needs to be left intact and operational for use, it inevitably provides a "backdoor" that can be exploited to undermine the security of the chip. Potential attackers can then use the JTAG to dump critical data or reverse engineer IP cores, for example. Since an attacker will use the JTAG differently from a legitimate user, it is possible to detect the difference using machine-learning algorithms. A JTAG protection scheme, SLIC-J, is proposed to monitor user behavior and detect illegitimate accesses to the JTAG. Specifically, JTAG access is characterized using a set of specifically-defined features, and then an on-chip classifier is used to predict whether the user is legitimate or not. To validate the effectiveness of the approach, both legitimate and illegitimate JTAG accesses are simulated using the OpenSPARC T2 benchmark. The results show that the detection accuracy is 99.2%, and the escape rate is 0.8%.

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Analog neural network design for RF built-in self-test

Cited by 27 publications

References 27 publications

Post-deployment trust evaluation in wireless cryptographic ICs

Post-deployment trust evaluation in wireless cryptographic ICs

Self-Testing Analog Spiking Neuron Circuit

Detection of Illegitimate Access to JTAG via Statistical Learning in Chip

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