Analysis and design considerations of systematic nonlinearity for sigma-delta current-steering DAC

Abstract

This paper deals with the design aspect of currentsteering D/A converters which is to be incorporated in an oversampling sigma-delta DAC with Dynamic Element Matching (DEM), and particularly with the trade-off between device sizing, output impedance, and ideal systematic nonlinearity. A formula for the estimation of minimum output impedance requirement based on DNL specification is proposed, and the corresponding design guideline is given. As a case study, a 16-bit sigma-delta current-steering DAC is presented. It is shown in this paper that basic cascode current mirror structure is not practical for this purpose. An 8-level current steering DAC with 16-bit accuracy was designed in a 0.18-ȝm CMOS process using the regulated cascode enhanced output impedance current mirror. A worst case INL of 0.09 LSB of a 16-bit converter was achieved.I.

Design and analysis of 8 bit fully segmented digital to analog converter

“…Total 255 current cells are needed in design of 8-bit unary segmented current steering DAC. Proper matching of current sources in current cell array provides lower glitches [6]. The value of output current or voltage across output load resistor depends on the applied digital input data which steered in the form of current from current source to output.…”

Design and Analysis of CMOS Thermometer Current Steering DAC to Remove Non-Linearity

“…To reduce the impact of non-linearities, the bits of thermometer coded D/A converter are increased with the assistance of higher order of binary to thermometer decoder. The main challenge is to implement the design achieving static linearity [1]. Mismatch between current sources is basic reason of non-linearity in current steering digital to analog converter which is disseminated by environmental and process variations [2].…”