Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops

Abstract

Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for low-jitter clock-frequency multiplication. Unfortunately, the coarse quantization of phase error makes these systems prone to the generation of limit cycles appearing as unwanted spurs in the spectrum. The random noise contributed by building blocks and acting as dithering signal can eliminate those spurs. The quantitative analysis of those phenomena becomes more involved when a DCO with relaxed intrinsic resolution, such as a ΔΣ-DCO is employed, and when practical spectra of random noise sources are considered. In this work, the expression of jitter is calculated in closed-form taking into account the quantization, introduced by both phase detector and DCO, and the phase noise of DCO, with both 1/f^2 and 1/^3 components. Combining these results, a closed-form expression of the total output jitter as a function of loop parameters and noise sources is developed which suggests a minimum-jitter design strategy. The proposed analysis and optimization are validated both numerically and experimentally on a 320-MHz digital bang-bang PLL fabricated in a 65-nm CMOS process

Influence of Jitter on Limit Cycles in Bang-Bang Clock and Data Recovery Circuits

“…This algorithm calculates the input jitter σ in as a function of the limit cycle amplitude A e and consists of the following steps: firstly, the Subsequently, the amplification factor K * s that causes a limit cycle is determined according to Eq. (14). Thereafter, the amplitude of the limit cycle A e is swept.…”

“…However, most of the previously published work focuses on the domain of digital BB-PLL [9]- [14] and very little M. Verbeke, A. Vyncke and G. Torfs are with the Department of Information Technology (INTEC), Ghent University -iMinds -imec, 9000 Gent, Belgium (e-mail: marijn.verbeke@intec.ugent.be; arno.vyncke@intec.ugent.be; guy.torfs@intec.ugent.be).…”

Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs

“…In recent applications, ADPLLs are interconnected into trees or networks to generate a synchronised distributed signal [1]- [9]. The research on ADPLLs and their networks is driven by the following major issues: how to ensure the synchronisation and stability of a single ADPLL or a network [10]- [15] and how to minimise their jitter [16]- [25]. To address these issues, one should have a greater theoretical insight into the behaviour of the system.…”

Cycle-slipping pull-in range of bang-bang PLLs

“…There is a lot of literature dealing with the smallsignal steady-state behavior of bang-bang PLLs [2], [3]. Those works focus on the jitter performance and stability of such PLLs.…”