Analysis of a Novel Metal Implant Junctionless Tunnel FET for Better DC and Analog/RF Electrostatic Parameters

Tirkey, Sukeshni; Sharma, Dheeraj; Yadav, Dharmendra Singh; Yadav, Shivendra

doi:10.1109/ted.2017.2730922

Cited by 74 publications

(20 citation statements)

References 31 publications

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“…Another crucial RF parameter maximum oscillating frequency (f max ) is expressed as the frequency at which value of power gain of the device is unity [26]. f max is expressed as:…”

Section: Resultsmentioning

confidence: 99%

A comparative investigation of low work‐function metal implantation in the oxide region for improving electrostatic characteristics of charge plasma TFET

Aslam

Sharma

Yadav

et al. 2019

Micro & Nano Letters

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Abruptness at tunnelling junction is a vital issue with doped tunnel field-effect transistor (TFET) to achieve improved electrostatic characteristics. This task is more problematic for charge plasma TFET (CP-TFET) because of large tunnelling barrier at the channel/source interface. In this regard, an effective approach has already been employed through implantation of a horizontal metallic splint (HMS) inside the dielectric region near channel/source joint for improved electrical behaviour of CP-TFET. However, placement of a vertical metal splint (VMS) provides contact for HMS and gate electrode, which gives magnificent analogue/DC characteristics for newer structure. Combination of HMS and VMS (i.e. double metal splint (DMS)) increases electron density at channel/source junction for improved electron tunnelling rate compared with only HMS structure. In this regard, a complete comparative analysis of DMS CP TFET (DMS-CP-TFET) is performed between CP-TFET and HMS-CP-TFET. Furthermore, consequence of length and work-function variation of DMS and HMS on DC/RF parameters is investigated in device optimisation part of this work.

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“…Another crucial RF parameter maximum oscillating frequency (f max ) is expressed as the frequency at which value of power gain of the device is unity [26]. f max is expressed as:…”

Section: Resultsmentioning

confidence: 99%

A comparative investigation of low work‐function metal implantation in the oxide region for improving electrostatic characteristics of charge plasma TFET

Aslam

Sharma

Yadav

et al. 2019

Micro & Nano Letters

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“…To resolve this issue, various design improvements have been proposed [11]- [18]. In [11], the Ge/Si heterojunction is proposed, and a U-shaped gate with an n+ pocket is introduced to enhance the tunneling efficiency.…”

Section: Introductionmentioning

confidence: 99%

A Novel Planar Architecture for Heterojunction TFETs With Improved Performance and Its Digital Application as an Inverter

Yang

et al. 2020

IEEE Access

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A novel planar architecture is proposed for tunnel field-effect transistors (TFETs). The advantages of this architecture are exhibited, taking the InAs/Si TFET as an example, and the effects of different device parameters are analyzed in detail. Owing to the gate field being parallel to the tunneling interface, the gate control is enhanced, and a better electrical performance is obtained. Moreover, different from a conventional TFET, in which the effective tunneling area and current can hardly be modulated by the gate length, in our proposed device, the effective tunneling area and current can be adjusted depending on the actual requirements of circuit design, which increases the flexibility of TFET-based circuit design. In addition, the device architecture can also be extended to other materials, such as Ge/Si and GaSb/InAs, and thus be used for both n-type and p-type devices. The results show that the complementary digital inverter structure with InAs/Si as the n-type TFET and Ge/Si as the p-type TFET would be helpful for future ultralow power applications. This proposed structure without any complicated fabrication steps shows better compatibility with CMOS technology compared to other TFETs with heterojunction and structural innovations presented in theoretical works. INDEX TERMS Tunnel field-effect transistor, band-to-band tunneling, InAs/Si heterojunction, complementary TFET inverters.

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“…Recently, junctionless nanowire (JLNW) tunnel field-effect transistors (TFETs) are proposed as promising candidates to replace conventional MOSFETs in the future [2][3][4][5]. The working principle of n-doped JLNW TFETs is as follows: when the positive gate voltage is applied, the conduction band in the channel region is aligned with the valence band in the source region, forming a tunnelling window at the source/channel interface and allowing carriers to tunnel from the source to the channel region.…”

Section: Introductionmentioning

confidence: 99%

“…Rahimian and Fathipour [17] studied the influence of the hetero-gate dielectric on the JLNW TFET. Tirkey et al [18] analysed the DC and RF characteristics of the metal implant JLNW TFET. Wang et al [19] investigated the performance of the uniaxially strained FinTFET using technology computer-aided design (TCAD) simulations.…”

Section: Introductionmentioning

confidence: 99%

Analytical drain current model of strained junctionless nanowire tunnel field‐effect transistor fabricated on virtual substrate

Zhang

2020

IET Circuits, Devices & Systems

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Analysis of a Novel Metal Implant Junctionless Tunnel FET for Better DC and Analog/RF Electrostatic Parameters

Cited by 74 publications

References 31 publications

A comparative investigation of low work‐function metal implantation in the oxide region for improving electrostatic characteristics of charge plasma TFET

A comparative investigation of low work‐function metal implantation in the oxide region for improving electrostatic characteristics of charge plasma TFET

A Novel Planar Architecture for Heterojunction TFETs With Improved Performance and Its Digital Application as an Inverter

Analytical drain current model of strained junctionless nanowire tunnel field‐effect transistor fabricated on virtual substrate

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