2015
DOI: 10.7567/jjap.54.04dp05
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Analysis of effect of gate oxidation at SiC MOS interface on threshold-voltage shift using deep-level transient spectroscopy

Abstract: In this study, we investigate the influence of wet oxidation after nitridation of a gate oxide on the interface states in SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). We used deep-level transient spectroscopy (DLTS) to clarify the mechanism behind the positive shift in the threshold voltage after wet oxidation without any significant decrease in the mobility. We applied DLTS using a small pulse to obtain the depth profile of the states. We found that the density of deep-level states near t… Show more

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Cited by 3 publications
(2 citation statements)
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“…The wet oxidation is performed at a relative low temperature from 800 °C to 900 °C. The low temperature wet oxidation induces deep level states at the MOS interface which was investigated by DLTS measurement [13]. The deep states at around 0.68 eV contribute to the elevation of the threshold voltage and do not lower channel mobility.…”
Section: Large 12 Kv Sic-mosfet For Industrial Machines and Infrastru...mentioning
confidence: 99%
“…The wet oxidation is performed at a relative low temperature from 800 °C to 900 °C. The low temperature wet oxidation induces deep level states at the MOS interface which was investigated by DLTS measurement [13]. The deep states at around 0.68 eV contribute to the elevation of the threshold voltage and do not lower channel mobility.…”
Section: Large 12 Kv Sic-mosfet For Industrial Machines and Infrastru...mentioning
confidence: 99%
“…Accurate analysis of the D it at the SiO 2 /SiC interface is essential for correctly evaluating the oxide quality, which is related to the electrical characteristics of SiC MOSFETs. Several techniques [1][2][3][4] have been applied to evaluate the interface states at the SiO 2 /SiC interface experimentally by using MOS capacitor. Conductance method at lower temperature is used for quantitatively evaluating the energy distribution of the D it at MOS interface closer to the conduction band edge [5][6][7][8].…”
Section: Introductionmentioning
confidence: 99%