Analysis of the impact of process variations on clock skew

Abstract

In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as VT and IDSS, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution networ

Reducing clock skew variability via cross links

“…The variation factors include manufacturing process variations [5,6], power/ground noise [7] and ambient temperature variations. The unwanted skew variations are not only harmful to timing performance but also difficult to control, because reliable estimations on the variations are generally not available during the stage of clock network design.…”

Buffered clock tree for high quality IC design

“…Similarly, T 3 is merged with T 4 at node v 6 . Since t 3 and t 4 are much greater than t 1 and t 2 , it is quite possible that t 6 is much greater than t 5 and another wire snaking results from merging subtree T 5 with T 6 at node v 7 .…”

“…We can compare this merging with T 6 +T 5 ; v 7 in Figure 1(b), since both mergings start from v 6 . On one hand, there is less imbalance on delay-targets for merging T 6 + T 2 ; v 8 since t 6 − t 2 < t 6 − t 5 . On the other hand, as C 2 < C 5 , the merging T 6 + T 2 ; v 8 has greater imbalance on load capacitance which makes it easier to achieve imbalanced delay-targets without wire snaking.…”

“…Third, due to its large size, the switching of clock signal may draw huge current from power/ground network and incur power supply noise. Last but not least, clock signal is vulnerable to process variations [4,5] and the induced clock signal variation may in term affect circuit design and timing. Therefore, it is vitally important to have a clock layout algorithm addressing these concerns for a high quality integrated circuit design.…”

Characterisation of FPGA Clock Variability

“…These include work employing Monte Carlo simulations [3,10] as well as approaches based on canonical or numerical analysis of the classical H-tree clock structure [1,2]. To date, there is no published report on the measurement or analysis of clock tree variability in FPGAs.…”