In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as VT and IDSS, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution networ

The impact of process fluctuations on the variability of deep submicron (DSM) very large scale integration (VLSI) circuit performances is investigated in this paper. In particular, we show that as process dimensions scale down in the subhalfmicron region, the relative weight of process variability tends to increase, thus wearing down a non negligible portion of the benefits that are expected from minimum feature size scaling. We will show that in order to better exploit the advance of process technology, it is essential to adopt a realistic approach to worst case modeling, as the one described in [1] [assigned probability technique (APT)]. The application of the APT technique to different test circuits designed in 0.35, 0.25, and 0.18 m CMOS technologies with a power supply ranging from 3.3 V down to 1 V will demonstrate how the manufacturability of DSM designs is going to be a vital factor for the successful implementation of high-performance or low-power systems in 0.18 m and lesser technologies

No abstract

No abstract

No abstract