Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

Sharma, Vijender Kumar; Kumar, B. Dinesh; Illikkal, Muhammed Suhail; Tripathi, Jai Narayan; Gupta, Navneet; Shrimali, Hitesh

doi:10.1109/iscas.2019.8702313

Cited by 5 publications

(5 citation statements)

References 19 publications

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“…Due to this, the dynamic variations can be observed at the transition-edge. For calculation of PSIJ, the small-signal transfer analysis is very important [3], [4], [7]. Therefore, the proposed method can also be used for the estimation of PSIJ.…”

Section: A Applicability: the Ba-iam And The Inspection-based Methodsmentioning

confidence: 99%

“…For the AMS circuits, it may deteriorate voltage gain, signal-to-noise ratio (SNR), phase noise, effective number of bits (ENOB), spurious-free dynamic range (SFDR), etc. In the last few decades, rigorous work has been done to analyse the effect of deterministic supply noise for digital circuits [3]- [7]. However, very few works are reported to analyse the effects of these fluctuations on analog circuits [8]- [11].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix

Sharma

Tripathi

Shrimali

2020

IEEE Open J. Circuits Syst.

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This paper presents two methods, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittance matrix. The proposed methods are used to develop a generalised two-port network analysis for the commonly used amplifier topologies, in the presence of the supply, ground, bulk, and input noise sources. Various illustrative case studies (common-source, common-gate, and push-pull amplifiers) are considered to validate the analytical method of different CMOS technology nodes (180 nm, 110 nm, and 28 nm) and foundries (Lfoundry, UMC, and TSMC). Both the proposed methods are compared with the relevant existing methods in terms of mean percentage error (MPE), and computational complexity. The mathematically derived expressions using two methods show less than 4% MPE when compared with the schematic simulation results, obtained by the SPICE based simulations. Also, the post-layout simulations (PLS) results for all the examples (designed in CMOS 180 nm Lfoundry technology) show excellent matching with schematic simulations. The proposed methods can be further applicable to antennas, complex circuits, digital circuits, etc.

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Section: A Applicability: the Ba-iam And The Inspection-based Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix

Sharma

Tripathi

Shrimali

2020

IEEE Open J. Circuits Syst.

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“…The offset in the pre-amplification stage is primarily caused by device mismatches, such as the length-to-width ratio, channel mobility μ, and threshold voltage VT of symmetrical transistors, with the most significant impact arising from the matching of the differential input transistors. On the other hand, the mismatch in parasitic capacitances of internal nodes along the differential path also contributes to the offset [12]. Assuming the gate-source voltage, threshold voltage, and width-to-length ratio of MN1/MN2 are VGS, VT, β, and their mismatches are ΔVT, Δβ, with the capacitance of the FP/FN nodes as C and their mismatch as ΔC.…”

Section: Conventional Dynamic Comparatormentioning

confidence: 99%

A full-scale complementary dynamic comparator

Xi,

Li,

Diao

et al. 2024

J. Phys.: Conf. Ser.

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This paper presents a dynamic comparator that achieves precise comparison across the entire full-scale range. The comparator, an essential component module in analog-to-digital converters (ADCs), is influenced by its input signal range, speed, and offset voltage, all of which impact the ADC’s performance. In the proposed comparator, a pre-amplification stage using PMOS as the input is incorporated alongside the comparator utilizing NMOS as the input, creating a complementary structure. This design ensures that at least one pre-amplification stage operates effectively, thereby maintaining the accuracy of the comparator as the input signal varies across the entire full-scale voltage range (0 to VDD). Through sound circuit design, the proposed comparator effectively avoids introducing additional distortion and noise. The performance of the comparator is verified under the 180 nm process. The comparator achieves accurate comparison across the entire full-scale range, with a standard deviation σ of the input offset voltage of 6 mV, noise of 450 uV, and a layout area of 467.36 um2. Simulation results demonstrate that the comparator exhibits excellent performance, providing stability assurance for the ADC and extending the ADC’s input signal range.

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“…In the process of determining the closed-form expression for the PSIJ, knowledge of transfer function (TF) is essential in the presence of deterministic supply noise sources. Note that, most of the PSIJ methods are directly or indirectly based on the supply-to-output TF [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32]. Among these methods, an efficient method for PSIJ (EMPSIJ) method is a better choice in terms of computational efforts.…”

Section: Introductionmentioning

confidence: 99%

“…The TF analysis in the reported works is based on the conventional nodal analysis which can be further simplified using the Thomas algorithm, symbolic admittance method, etc. in [27], [28]. However, these methods are a bit time consuming as they require a large number of expressions and matrix elements to solve the final expression including the PSN, GSN, and the BSN.…”

Section: Introductionmentioning

confidence: 99%

Indefinite Admittance Matrix Based Modelling of PSIJ in Nano-Scale CMOS I/O Drivers

Sharma

Tripathi

Shrimali

2022

IEEE Open J. Nanotechnol.

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The past decade has witnessed a tremendous reduction in the feature size from the deepsubmicron to the advanced nano-scale CMOS devices. In nanoscale devices based high-speed systems, the budgeting of jitter due to supply fluctuations is one of the major performance bottlenecks while designing integrated circuits (ICs). In this paper, an accurate and efficient method to analyse power supply induced jitter (PSIJ) in CMOS N-stage inverters is developed using the estimation-by-inspection method. Based on the Indefinite Admittance Matrix, a reduced two-port network is developed for a multiple-input circuit, considering the presence of the supply/bulk/ground sources. The closed-form expressions of the PSIJ have been evaluated for a single and N-stages CMOS inverter chain. The expression is also valid for the PSIJ analysis at any intermediate stage of the N-stage chain. For validation purpose, the circuits are designed in a standard 28 nm CMOS technology with V DD of 1 V. The analytical results are compared with the simulation and the experiments. The maximum mean percentage error for EDA simulation and experimentally measured results are 2.4% and 13%, respectively. The proposed analysis is compared with some of the existing PSIJ modelling techniques and shows a significant improvement in speed-up factor and error percentage.INDEX TERMS Two-port network, indefinite admittance matrix (IAM), power supply induced jitter (PSIJ), nano-scale devices.

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Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

Cited by 5 publications

References 19 publications

Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix

Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix

A full-scale complementary dynamic comparator

Indefinite Admittance Matrix Based Modelling of PSIJ in Nano-Scale CMOS I/O Drivers

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