Analytical modelling of a Cyl-JLAM MOSFET in the subthreshold region using distinct device geometry

Misra, Sarita; Biswal, Sudhansu Mohan; Baral, Biswajit; Swain, Sanjit Kumar; Sarkar, Angsuman; Pati, Sudhansu Kumar

doi:10.1007/s10825-020-01560-z

Cited by 3 publications

(3 citation statements)

References 44 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, the proposed device can be preferred over Junction-less Double Gate MOSFET for high-speed [37][38][39][40] and lowpower consumption applications in the subthreshold regime as a possible candidate to replace conventional CMOS devices 11 (c). From 11 (d), it is obvious that in the sub-threshold regime, significant logic swing [41][42] can be obtained which also proves the efficacy of the device in the sub-threshold regime [43][44][45][46][47][48].…”

Section: Cmos Inverter Based On the Proposed Devicementioning

confidence: 74%

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Mukherjee,

Ghosh,

Debnath

et al. 2024

JICS

View full text Add to dashboard Cite

In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

show abstract

Section: Cmos Inverter Based On the Proposed Devicementioning

confidence: 74%

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Mukherjee,

Ghosh,

Debnath

et al. 2024

JICS

View full text Add to dashboard Cite

show abstract

“…The trade-off between gain and bandwidth is calculated by Gain Bandwidth Product (GBW) [27,28]. For semiconductor devices it is defined as GBW= gm / (20*pi* Cgd)…”

Section: Fig 9 Fmax ~ Vgs Curve With Varying Oxide Layer Thicknessmentioning

confidence: 99%

Influence of oxide thickness variation on analog and RF performances of SOI FinFET

Tripathy

Acharya

Rout³

et al. 2022

FACTA U EE

View full text Add to dashboard Cite

This paper focuses on the impact of variation in the thickness of the oxide (SiO2) layer on the performance parameters of a FinFET analysed by varying the oxide layer thickness in the range of 0.8nm to 3nm. While varying the oxide layer thickness, the overall width of the FinFET is fixed at a value 30nm, and the FinFET parameters are analysed for structures with different oxide layer thickness. The parameters like drain current, transconductance, transconductance generation factor, parasitic capacitances, output conductance, cut-off frequency, maximum frequency, GBW, energy and power consumption are calculated to study the influence of FinFET oxide (SiO2) layer thickness variation. It is detected from the result and analysis that the drain current, transconductance, transconductance generation factor, gain bandwidth and output conductance improve with decrement in oxide layer thickness whereas, the parasitic capacitances, cut-off frequency and maximum frequency degrade when there is a reduction in oxide (SiO2) layer thickness. The parameters like energy and consumed power of FinFET get better when the oxide (SiO2) layer thickness increases.

show abstract

“…So, the device with lower values of oxide layer thickness possesses lesser maximum frequency compared to the device with higher oxide layer thickness. The trade-off between gain and bandwidth is calculated by Gain bandwidth product (GBW) [37,38]. For semiconductor devices it is defined as,…”

Section: Analog Performancesmentioning

confidence: 99%

Influence of Variation in Oxide layer Thickness on Analog and RF performances of SOI FinFET

Tripathy

Pk³

2021

Preprint

View full text Add to dashboard Cite

In this paper, the influence of oxide (SiO2) layer thickness on the different figure of merits of a FinFET is analysed by varying the oxide layer thickness which is present between the gate and the Fin. Here, the overall thickness of the FinFET is taken to be 30nm, and the oxide (SiO2) layer thickness is changed from 0.8 nm to 3nm, and the analog, radio frequency parameters are determined for different structures. The performance parameters like drain current (ID), transconductance generation factor (TGF), transconductance (gm), output conductance (gds), parasitic capacitances like Cgs, Cgd, Cgg, cut-off frequency (fT), gain bandwidth product (GBW) and maximum frequency of oscillation (fmax) are calculated to learn the influence of variation in the FinFET oxide (SiO2) layer thickness. It is detected from the result and analysis that the drain current, output conductance, transconductance generation factor, transconductance and gain bandwidth product improve with decrement in oxide layer thickness. But as a tradeoff, the internal capacitances like Cgs, Cgd, Cgg, maximum frequency of oscillation and cut-off frequency degrade when there is a reduction in oxide (SiO2) layer thickness.

show abstract

Analytical modelling of a Cyl-JLAM MOSFET in the subthreshold region using distinct device geometry

Cited by 3 publications

References 44 publications

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Influence of oxide thickness variation on analog and RF performances of SOI FinFET

Influence of Variation in Oxide layer Thickness on Analog and RF performances of SOI FinFET

Contact Info

Product

Resources

About