2012
DOI: 10.1016/j.mejo.2011.12.011
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Analytical optimization of high-performance and high-yield spiral inductor in integrated passive device technology

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Cited by 34 publications
(15 citation statements)
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“…The IPD has the advantages of being a simplified model, having a reduced size, and enhanced performance, benefiting from the reduction of parasitic effects compared with standard discrete systems [8,9]. Moreover, the Q-factor used to evaluate device performances is low for lumped elements but can be enhanced using IPD technology as reported in our previous studies [10][11][12]. GaAs substrates have become the second most important semiconductor materials owing to their high saturated electron drift velocity, low field mobility, low parasitics, and good interdevice isolation.…”
Section: Introductionmentioning
confidence: 98%
“…The IPD has the advantages of being a simplified model, having a reduced size, and enhanced performance, benefiting from the reduction of parasitic effects compared with standard discrete systems [8,9]. Moreover, the Q-factor used to evaluate device performances is low for lumped elements but can be enhanced using IPD technology as reported in our previous studies [10][11][12]. GaAs substrates have become the second most important semiconductor materials owing to their high saturated electron drift velocity, low field mobility, low parasitics, and good interdevice isolation.…”
Section: Introductionmentioning
confidence: 98%
“…Therefore, IPD-based implementation of high-performance, miniaturized resonators has recently garnered an increased amount of interest from researchers [ 4 , 5 , 6 ]. IPDs typically combine a number of passive components into a single package.…”
Section: Introductionmentioning
confidence: 99%
“…Various on-chip inductors are proposed in the literature such as planar inductors, Planar inductors with pattern ground shield, Symmetric inductors, series stacked inductors and pyramidal up down structures. Planar inductors [3] suffer from low Q factor, Low Q-factor is due to the resistive-capacitive losses on the silicon substrate, and also area constraints limit the inductance value. Pattern ground shield [4] is used to improve the Q factor in the cost of improved fabrication cost.…”
Section: Introductionmentioning
confidence: 99%