Anomalous low-voltage tunneling current characteristics of ultrathin gate oxide (∼2 nm) after high-field stress

Abstract

The effect of oxide barrier shape change caused by stress-induced interface trap charges on the low-voltage tunneling current ͑LVTC͒ characteristics of ultrathin gate oxide ͑ϳ2 nm͒ is studied in this work. It was found that for an ultrathin gate oxide working in the direct tunneling regime, the LVTC behavior is strongly dependent on the barrier shape of the oxide. After high-field stress, anomalous LVTC phenomenon is observed. There is an invariant point existing in current-voltage curves. For a bias smaller than the value of the invariant point, the gate current decreases with stress time. However, for a bias larger than that, the gate current increases with stress time and then saturates. This phenomenon cannot be explained by conventional trap-assisted tunneling conduction, but by the change of tunneling probability due to barrier shape variation. An interface trap charge model is proposed to explain the observed invariant point mentioned above. From this, one can find the voltage corresponding to the midgap bias and, therefore, the initial effective oxide charge number density.

Oxide Wearout, Breakdown, and Reliability

“…For other applications the final destructive breakdown event is the important one. In ultra-small devices with ultra-thin oxides, where the stored energy in the capacitor, 1/2 CV 2 may be too low to trigger thermal breakdown, direct tunneling currents, SILCs, and the accompanied power dissipation is probably the most important criteria defining oxide and IC reliability [96,98,237,291,392,[794][795][796][797][798][799][800][801][802]. Dynamic random access memories need a fixed amount of charge stored, and, as the storage area decreases, this requirement leads to the need for high dielectric constant materials or complicated schemes for producing larger area devices while keeping the surface area minimal.…”

Oxide Wearout, Breakdown, and Reliability

“…For other applications the final destructive breakdown event is the important one. In ultra-small devices with ultra-thin oxides, where the stored energy in the capacitor, 1/2 CV 2 may be too low to trigger thermal breakdown, direct tunneling currents, SILCs, and the accompanied power dissipation is probably the most important criteria defining oxide and IC reliability [96,98,237,291,392,[794][795][796][797][798][799][800][801][802]. Dynamic random access memories need a fixed amount of charge stored, and, as the storage area decreases, this requirement leads to the need for high dielectric constant materials or complicated schemes for producing larger area devices while keeping the surface area minimal.…”

Comparison of interfaces states density through their energy distribution and LVSILC induced by uniform and localized injections in 2.3nm thick oxides

“…In ultra-thin oxides, a gate leakage current is measured in depletion regime. This leakage current increases with stress and is referred to as LVSILC (low voltage stress induced leakage current) [1][2][3][4][5][6][7]. In previous papers [3,7], it has been shown that the LVSILC normalized variation presents two degradation peaks.…”

“…According to [1], the gate current measured in depletion regime before and after stress [2] is due to a conduction mechanism through interface states. It is then interesting to compare the interface state density variation with the LVSILC one.…”