Application of neural networks with CSD coefficients for human face recognition

Parvin, Azadeh; Ahmadi, Majid; Muscedere, Roberto

doi:10.1109/iscas.2013.6572174

Cited by 5 publications

(3 citation statements)

References 31 publications

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“…The SD representation has been used to reduce the time of execution of the multipliers used, for example, in an artificial neural network (ANN) inference phase as in [52], or to reduce the hardware complexity of multipliers used in an FPGA implementation of an ANN architecture as in [53], but also in many other efficient VLSI implementations [54][55][56][57].…”

Section: Amentioning

confidence: 99%

An Overview of Systolic Arrays for Forward and Inverse Discrete Sine Transforms and Their Exploitation in View of an Improved Approach

2022

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This paper aims to present a unified overview of the main Very Large-Scale Integration (VLSI) implementation solutions of forward and inverse discrete sine transforms using systolic arrays. The main features of the most important solutions to implement the forward and inverse discrete sine transform (DST) using systolic arrays are presented. One of the central ideas presented in the paper is to emphasize the advantages of using regular and modular systolic array computational structures such as cyclic convolution, circular correlation, and pseudo-band correlation in the VLSI implementation of these transforms. The use of such computational structures leads to architectures well adapted to the features of VLSI technologies, with an efficient use of the hardware structures and a reduced I/O cost that helps avoiding the so-called I/O bottleneck. With the techniques presented in this review, we have developed a new VLSI implementation of the DST using systolic arrays that allow efficient hardware implementation with reduced complexity while maintaining high-speed performances. Using a new restructuring input sequence, we have been able to efficiently reformulate the computation of the forward DST transform into a special computational structure using eight short quasi-cycle convolutions that can be computed with low complexity and where some of the coefficients are identical. This leads to a hardware structure with high throughput. The new restructuring sequence is the use of the input samples in a natural order as opposed to previous solutions, leading to a significant reduction of the hardware complexity in the pre-processing stage due to avoiding a permutation stage to reverse the order. Moreover, the proposed VLSI architecture allows an efficient incorporation of the obfuscation technique with very low overheads.

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Section: Amentioning

confidence: 99%

An Overview of Systolic Arrays for Forward and Inverse Discrete Sine Transforms and Their Exploitation in View of an Improved Approach

2022

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“…In [3] and [4], the authors show different techniques for the implementation of low power interconnects by using Canonical Signed Digit Number System and the Binary Coded Canonical Digit Signed Digit. In [5], the authors use Canonical Signed Digit (CSD) coding to reduce the time of execution of the multiplications that are massively used in the ANN inference phase, while in [6], an ANN architecture is implemented on FPGA using CSD-based multipliers obtaining a reduction in hardware resources.…”

Section: Introductionmentioning

confidence: 99%

Approximated Canonical Signed Digit for Error Resilient Intelligent Computation

Cardarilli

Nunzio

Fazzolari

et al. 2019

2019 53rd Asilomar Conference on Signals, Systems, and Computers

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Lowering the energy consumption in applications operating on large datasets is one of the main challenges in modern computing. In this context, it is especially important to lower the energy required to transfer data from/to the memory. Usually, this is obtained by applying smart encoding techniques to the data. In this work, we show how to reduce the switching activity in buses and floating-point units by an approximated canonical signed-digit encoder. The precision of the encoding is programmable and can be chosen depending on the application's required accuracy.

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“…[1]- [3]. Canonical signed digit (CSD) is one of the MSD coding method with the requirement that the nonzero digit cannot be adjacent, which makes it unique and efficient in reducing the number of additions in the accumulations.…”

Section: Introductionmentioning

confidence: 99%

A fast and energy efficient binary-to-pseudo CSD converter

Zhang

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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The canonical signed digit (CSD) coding is widely used in digital arithmetic operations due to its property that there is no adjacent nonzero digits in the encoded numbers. However, the benefits of the CSD coding may be faded because of the recursive conversion process from the binary representations. This paper presents a novel pseudo CSD coding method, which takes the merits of CSD, while simplifies the conventional conversion process. The simulation results indicate that the proposed converter can achieve at least 31.8% speed improvement and 42.9% energy reduction for a 16-bit binary operand at 1.2V in a 0.13-μm CMOS technology. It could run even faster than the competitors when the operand length increases.

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Application of neural networks with CSD coefficients for human face recognition

Cited by 5 publications

References 31 publications

An Overview of Systolic Arrays for Forward and Inverse Discrete Sine Transforms and Their Exploitation in View of an Improved Approach

An Overview of Systolic Arrays for Forward and Inverse Discrete Sine Transforms and Their Exploitation in View of an Improved Approach

Approximated Canonical Signed Digit for Error Resilient Intelligent Computation

A fast and energy efficient binary-to-pseudo CSD converter

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