Approach to suppress ambipolar conduction in Tunnel FET using dielectric pocket

Abstract

The impact of high-k dielectric pocket (DP) on the ambipolar conduction of tunnel field-effect transistors (TFETs) is demonstrated using two-dimensional Technology Computer Aided Design (TCAD) simulations. In the proposed structure of TFETs, an optimised portion of the upper drain region is replaced with a high-k DP at the channel-drain interface. It is demonstrated that due to the enhancement of the depleted drain region under DP, the minimum tunnelling width at channel-drain interface increases, and attains a maximum value for an optimum length and thickness of DP. Eventually, this increment in the minimum tunnelling width leads to a significant reduction in ambipolar conduction in TFETs. Furthermore, it is shown that performance parameters including the ON-state current, subthreshold swing and output characteristics are not affected by the presence of the proposed DP. Even, the gate-to-drain capacitance is reduced with the inclusion of DP at the channel-drain interface, thus leading to an improved cutoff frequency of TFETs. Moreover, it is also demonstrated that only a 10 nm of gate-on-drain overlapping along with this DP is capable of eliminating the ambipolarity completely for even a higher gate voltage of −0.8 V.

Drain Current Model for a Single Gate Tunnel Field Effect Transistor with Hetero-Dielectric Gate (HDG)

“…However, main concern for this technique is that one has to choose appropriate work function for auxiliary gate to overcome both drawbacks at the same time. Chandan Kumar Pandey et al [26] has proposed dielectric pocket in TFET to suppress the ambipolar conduction. In this technique, they have replaced the upper portion of drain region with high κ-DP (dielectric pocket) at the channel-drain interface which increases the minimum tunneling width and hence suppresses the ambipolar current on the cost of on-current.…”

Performance Improvement of Heterojunction Double Gate TFET with Gaussian Doping

“…Regardless of all these advantages, TFET is dealing with some major issues that correspond to reduced drain current, ambipolar state conduction, and deficient high-frequency performance [8][9][10][11]. Many researchers have introduced several techniques such as gate overlapping on the drain region [12], using hetero gate dielectric [13], tunneling junction engineering [14], gate work function engineering [15], and the introduction of pocket layer [16,17] to raise the ON-state current of all silicon TFETs.…”

Suppression of ambipolarity in tunnel‐FETs using gate oxide as parameter: analysis and investigation

“…The limitation posed by the low ON-state current can be somehow solved by the use of source pocket TFET or p-n-p-n TFET, appropriate heterostructures, high k dielectrics, by engineering tunnelling-region, by using novel materials in the channel/source regions and so on [5][6][7][8][9][10][11][12][13][14][15][16]. On the other hand, to ease the ambipolar behaviour, various techniques have been proposed such as asymmetric source/drain doping, gate-drain overlap/underlap, nonuniform drain doping, spacer engineering, lateral heterostructure with high bandgap material at drain side, work function engineering of gate material, inclusion of the pocket at the drain side and so on [17][18][19][20][21][22][23]. Though these strategies decrease ambipolar current, they must be acknowledged at the expense of increased fabrication complexity or decreased ON-state current.…”