Architectural approaches to reducing power related system costs

Abstract

503) 712-2886The power dissipation of modern processors is steadily increasing, keeping pace with growing transistor counts and increasing clock frequencies. In an effort to counteract this trend, integrated circuit designers are aggressively employing design optimizations to minimize circuit power consumption. Power reduction was a key focus of the Intel Pentiurn@ 4 processor design team, and the design team focused from the beginning on reducing power consumption without compromising other design targets. Many techniques, both innovative and pre-existing, were applied across all functional units in the processor in an effort to eliminate unnecessary power consumption. The mass adoption of these techniques resulted in a significant reduction in both maximum and typical processor power dissipation.While these power reduction techniques can significantly improve power efficiency, the laws of physics dictate that, all else being equal, power consumption will be a constraint on product design as long as we continue on the trend lines indicated by Moore's Law. Minimizing the system cost resulting from the increasing power consumption will require focus and coordination between the platform and the processor.While we tend to think of integrated circuit power consumption as a single value, there are actually a number of parameters that we are concerned with when designing a system. Over very long time periods (hours to years), it is the average power consumption that impacts battery life in portable platforms, and determines reliability constraints in all systems. When we set the thermal dissipation requirements, we are most interested in the average power consumption over millisecond to second time periods. Power supply requirements are dictated by the power consumed over a few microseconds. The design of the power delivery network is constrained by the variation in current demand on nanosecond to microsecond time scales.If you examine the impact of the common power reduction techniques, you will note that some of these techniques reduce the power consumed during the execution of all workloads executed by the processor, while others have a much greater impact on specific workloads. For example, reducing the capacitance on the global clock distribution network will reduce the power consumed while executing any workload. In contrast, turning off the clock to an idle logic block will only provide a benefit on a workload on which that logic block is idle. As a result, the variation in power consumption over time is increasing. This is true both for different sections of a given workload, and from one workload to another. This variation in power consumption across workloads impacts many of the power related design decisions. For example, turning off the clock signal to idle functional units will reduce average power consumption, hence reducing the cost of the thermal solution. However, the same design feature may complicate the design of the power delivery network, since it now has to deal with rapid changes in the current...