Architecture and implementation of an associative memory using sparse clustered networks

Jarollahi, Hooman; Onizawa, Naoya; Gripon, Vincent; Gross, Warren J.

doi:10.1109/iscas.2012.6271922

Cited by 24 publications

(20 citation statements)

References 6 publications

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“…-architectures based on the original GBNN model [Jarollahi et al 2012] are referred as V0; -architectures based on the fully binary model we proposed are referred to as V1.0; -architectures based on binary model and triangular synaptic weight matrices are referred to as V1.1; -architectures based on binary model and cluster-based serialization are referred as V1.2; -architectures based on binary model and neuron-based serialization are referred as V1.3.…”

Section: Methodsmentioning

confidence: 99%

“…A fully parallel GBNN implementation, as proposed in Jarollahi et al [2012], requires a huge amount of wires to connect all the neurons and a large amount of computing logic to process data concurrently. Indeed, in the GBNN model, a neuron n i, j from a given 35:10 P. Coussy et al cluster j must be connected to all other neurons of all distant clusters.…”

Section: Serialized Communicationmentioning

confidence: 99%

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Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories

Coussy

Wouafo

Conde-Canencia

2015

J. Emerg. Technol. Comput. Syst.

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Brain processes information through a complex hierarchical associative memory organization that is distributed across a complex neural network. The GBNN associative memory model has recently been proposed as a new class of recurrent clustered neural network that presents higher efficiency than the classical models. In this article, we propose computational simplifications and architectural optimizations of the original GBNN. This work leads to significant complexity and area reduction without affecting neither memorizing nor retrieving performance. The obtained results open new perspectives in the design of neuromorphic hardware to support large-scale general-purpose neural algorithms.

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Section: Methodsmentioning

confidence: 99%

Section: Serialized Communicationmentioning

confidence: 99%

Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories

Coussy

Wouafo

Conde-Canencia

2015

J. Emerg. Technol. Comput. Syst.

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“…In this process the value of a neuron in other clusters does not affect that of one in the decoding cluster, hence the name. The conventional mapping process as described and implemented in [3]- [5] employs matrix multiplication to compute a score for each neuron followed by finding the maximum score and the winner-take-all rule.…”

Section: B Message Retrievalmentioning

confidence: 99%

Selective decoding in associative memories based on Sparse-Clustered Networks

Jarollahi

Onizawa

Gross

2013

2013 IEEE Global Conference on Signal and Information Processing

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Abstract-Associative memories are structures that can retrieve previously stored information given a partial input pattern instead of an explicit address as in indexed memories. A few hardware approaches have recently been introduced for a new family of associative memories based on Sparse-Clustered Networks (SCN) that show attractive features. These architectures are suitable for implementations with low retrieval latency, but are limited to small networks that store a few hundred data entries. In this paper, a new hardware architecture of SCNs is proposed that features a new data-storage technique as well as a method we refer to as Selective Decoding (SD-SCN). The SD-SCN has been implemented using a similar FPGA used in the previous efforts and achieves two orders of magnitude higher capacity, with no error-performance penalty but with the cost of few extra clock cycles per data access.

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“…with a good message retrieval ability (probability to retrieve a message). Based on binary units, binary connections and a simple decoding algorithm, this associative network model allows efficient fully-parallel hardware implementations [7,8,3]. However, like other models of associative networks [9], diversity strongly depends on the distribution of stored messages.…”

Section: Introductionmentioning

confidence: 99%

Restricted Clustered Neural Network for Storing Real Data

Danilo

Coussy

Conde-Canencia

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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Associative memories are an alternative to classical indexed memories that are capable of retrieving a message previously stored when an incomplete version of this message is presented. Recently a new model of associative memory based on binary neurons and binary links has been proposed. This model named Clustered Neural Network (CNN) offers large storage diversity (number of messages stored) and fast message retrieval when implemented in hardware. The performance of this model drops when the stored message distribution is non-uniform. In this paper, we enhance the CNN model to support non-uniform message distribution by adding features of Restricted Boltzmann Machines. In addition, we present a fully parallel hardware design of the model. The proposed implementation multiplies the performance (diversity) of Clustered Neural Networks by a factor of 3 with an increase of complexity of 40%.

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Architecture and implementation of an associative memory using sparse clustered networks

Cited by 24 publications

References 6 publications

Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories

Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories

Selective decoding in associative memories based on Sparse-Clustered Networks

Restricted Clustered Neural Network for Storing Real Data

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