Area-Dependent Photodetection Frequency Response Characterization of Silicon Avalanche Photodetectors Fabricated With Standard CMOS Technology

Lee, Myoung-Jae; Choi, Woo-Young

doi:10.1109/ted.2013.2240684

Cited by 42 publications

(25 citation statements)

References 16 publications

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“…We also reported 7 GHz-bandwidth CMOS-APD with the detection area of 20 × 20 µm 2 , the electrode spacing of 1 µm, and the PAD size for RF probing of 30 × 30 µm 2 [15]. The dependence of the bandwidth on the detection area has been reported by Lee et al [16] where enhancement of the bandwidth of the CMOS-APD up to 7.6 GHz was reported by reducing the device area to 10 × 10 µm 2 . In this paper, we will emphasize two main objectives; (1) investigation of the influence of the electrode spacing and the PAD size for RF probing as well as the detection area on the bandwidth of CMOS-APDs, and (2) discovering frequency response behavior of the CMOS-APDs at the low frequency region.…”

Section: Introductionmentioning

confidence: 94%

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

Napiah

Gyobu

Hishiki

et al. 2016

IEICE Trans. Electron.

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SUMMARYnMOS-type and pMOS-type silicon avalanche photodiodes (APDs) were fabricated by standard 0.18 µm CMOS process, and the current-voltage characteristic and the frequency response of the APDs with and without guard ring structure were measured. The role of the guard ring is cancellation of photo-generated carriers in a deep layer and a substrate. The bandwidth of the APD is enhanced with the guard ring structure at a sacrifice of the responsivity. Based on comparison of nMOS-type and pMOS-type APDs, the nMOS-type APD is more suitable for high-speed operation. The bandwidth is enhanced with decreasing the spacing of interdigital electrodes due to decreased carrier transit time and with decreasing the detection area and the PAD size for RF probing due to decreased device capacitance. The maximum bandwidth was achieved with the avalanche gain of about 10. Finally, we fabricated a nMOS-type APD with the electrode spacing of 0.84 µm, the detection area of 10 × 10 µm 2 , the PAD size for RF probing of 30 × 30 µm 2 , and with the guard ring structure. The maximum bandwidth of 8.4 GHz was achieved along with the gain-bandwidth product of 280 GHz.

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Section: Introductionmentioning

confidence: 94%

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

Napiah

Gyobu

Hishiki

et al. 2016

IEICE Trans. Electron.

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“…We also have previously reported a 10-Gb/s CMOS-Rx based on a CMOS-compatible avalanche photodetector (CMOS-APD) [21]. The CMOS-APD provides large photodetection bandwidth as well as enhanced responsivity [26], [27]. In [27], we identified that the photodetection bandwidth limiting factor of the CMOS-APD based on the P + /N-well junction is the diffusion transit time of holes photogenerated in the N-well region.…”

Section: Introductionmentioning

confidence: 98%

“…CMOS-PDs realized with standard CMOS technology are typically very slow due to slow diffusion photocurrents produced in the substrate as 850-nm light has much longer penetration depth than the narrow depletion regions possible in standard CMOS technology. Several approaches have been tried to overcome this limitation [17][18][19], [22][23][24][25][26][27]. Recently, a 10-Gb/s CMOS-Rx was reported with a high-speed spatially-modulated PD (SM-PD) [18].…”

Section: Introductionmentioning

confidence: 99%

“…The CMOS-APD provides large photodetection bandwidth as well as enhanced responsivity [26], [27]. In [27], we identified that the photodetection bandwidth limiting factor of the CMOS-APD based on the P + /N-well junction is the diffusion transit time of holes photogenerated in the N-well region. In this paper, we demonstrate that a higher-speed fully-integrated CMOSRx can be realized by employing a spatially-modulated CMOS-APD (SM-APD) that reduces the influence of hole diffusion.…”

Section: Introductionmentioning

confidence: 99%

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A fully-integrated 125-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

Lee¹,

Youn²,

Park³

et al. 2014

Opt. Express

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We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxidesemiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOScompatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

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“…With the development of sophisticated analog techniques to reduce front-end input impedance that interacts with the photodiode capacitance [2], the receiver speed is primarily determined by the optical bandwidth of the photodiode. Although there has been several demonstrations of high speed CMOS APDs aiming at small core-diameter fiberoptic communication [4], [5], the active photodetection area is too small for low cost VLC applications. In [4], it has been shown that the cut-off frequency of the APD decreases radically as the active area increases due to long diffusive path for photogenerated carriers.…”

Section: Introductionmentioning

confidence: 99%

Speed optimized large area avalanche photodetector in standard CMOS technology for visible light communication

Ray

Hella

Hossain

et al. 2014

IEEE SENSORS 2014 Proceedings

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This paper presents a speed-optimized large area avalanche photodetector (APD) in standard CMOS technology for visible light communication applications (VLC). Recent research efforts have reported high speed CMOS APDs with low breakdown voltage for considerably small photodiode sizes, which limits the APD usage in low cost optical receivers for VLC. The speed of a large-area APD dramatically decreases due to increased transit time of diffusive carriers in charge neutral regions. The proposed technique divides the active area into multiple subsections to decrease transit time and increase speed. A prototype 350×350 µm 2 APD is fabricated in 0.13-µm CMOS technology. The photodetector achieves a maximum gain of 7.6 K at 11 V reverse bias, showing excellent agreement with simulation results as calculated using the nonlocal impact ionization model based on recursive dead-space multiplication theory (DSMT). 2-D device level simulations validate the speed enhancement by comparing the small signal simulation results of three P+/N-well photodiodes with the same area detector composed of different number of sub-sections.

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Area-Dependent Photodetection Frequency Response Characterization of Silicon Avalanche Photodetectors Fabricated With Standard CMOS Technology

Cited by 42 publications

References 16 publications

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

A fully-integrated 125-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

Speed optimized large area avalanche photodetector in standard CMOS technology for visible light communication

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