Area-efficient FFT processor for MIMO-OFDM based SDR systems

Jang, Soohyun; Yang, Gi-Jung; Lee, Seongjoo; Jung, Yunho

doi:10.1587/elex.10.20130490

Cited by 3 publications

(4 citation statements)

References 5 publications

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“…In addition, it can support more flexible FFT lengths than the radix-4 or radix-8 algorithms, and is has double the throughput of the radix-2 3 algorithm. It is also suitable as an areaefficient variable-length FFT processor [38,39].…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

et al. 2021

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In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results. The processing steps for the RDA include range compression, range cell migration correction (RCMC), and azimuth compression. A matched filtering unit (MFU) and an RCMC processing unit (RPU) are required for real-time processing. Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU. The MFU reduces the memory requirements by applying a decimation-in-frequency (DIF) FFT and decimation-in-time (DIT) IFFT. The RPU provides a variable tap size and variable interpolation kernel. In addition, the MFU and RPU are designed to enable parallel processing of four 32-bit which are transferred via a 128-bit AXI bus. The proposed RDA-based SAR processor was designed using Verilog-HDL and implemented in a Xilinx UltraScale+ MPSoC FPGA device. After comparing the execution time taken by the proposed SAR processor with that taken by an ARM cortex-A53 microprocessor, we observed a 85-fold speedup for a 2048 × 2048 pixel image. A performance evaluation based on related studies indicated that the proposed processor achieved an execution time that was approximately 6.5 times less than those of previous FPGA implementations of RDA processors.

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Section: Introductionmentioning

confidence: 99%

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

et al. 2021

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“…With the rapid development of wireless communication systems, software defined radio (SDR) has been more attractive to support various applications such as WIFI, WCDMA, GSM, short-wave radio and radar [1,2,3]. Direct conversion receiver (DCR) architecture is the most common solution to SDR for its flexibility and reconfigurability [4].…”

Section: Introductionmentioning

confidence: 99%

“…The flow diagram of the DCOC method A DCOC procedure of LPF in the analog domainIEICE Electronics Express, Vol.16, No.19,[1][2][3][4][5][6] …”

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An effective DC offset calibration method combined with analog and digital circuits for direct conversion receivers

Wang¹,

Fan

Shen³

et al. 2019

IEICE Electron. Express

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This paper presents a DC offset calibration (DCOC) method combined with analog and digital circuits for direct conversion receivers. To work effectively, the LNA is shut off for better isolation and replaced by an equivalent resistance to keep the same transfer function of DC offset between calibration and operation. This method adopts DACs to compensate DC offset, then averages and eliminates the residual DC offset in the digital domain. Measurements show that this DCOC method achieves 0.44 mV DC offset and improves IM2 by 10 dB. The DCOC circuits occupy 0.23 mm 2 in 40 nm CMOS and consume 124 µA at 1.3 V supply.

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High-Speed Continuous Wavelet Transform Processor for Vital Signal Measurement Using Frequency-Modulated Continuous Wave Radar

Bae

Lee

Jung

2022

Sensors

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This paper proposes a high-speed continuous wavelet transform (CWT) processor to analyze vital signals extracted from a frequency-modulated continuous wave (FMCW) radar sensor. The proposed CWT processor consists of a fast Fourier transform (FFT) module, complex multiplier module, and inverse FFT (IFFT) module. For high-throughput processing, the FFT and IFFT modules are designed with the pipeline FFT architecture of radix-2 single-path delay feedback (R2SDF) and mixed-radix multipath delay commutator (MRMDC) architecture, respectively. In addition, the IFFT module and the complex multiplier module perform a four-channel operation to reduce the processing time from repeated operations. Simultaneously, the MRMDC IFFT module minimizes the circuit area by reducing the number of non-trivial multipliers by using a mixed-radix algorithm. In addition, the proposed CWT processor can support variable lengths of 8, 16, 32, 64, 128, 256, 512, and 1024 to analyze various vital signals. The proposed CWT processor was implemented in a field-programmable gate array (FPGA) device and verified through the measurement of heartbeat and respiration from an FMCW radar sensor. Experimental results showed that the proposed CWT processor can reduce the processing time by 48.4-fold and 40.7-fold compared to MATLAB software with Intel i7 CPU. Moreover, it can be confirmed that the proposed CWT processor can reduce the processing time by 73.3% compared to previous FPGA-based implementations.

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Area-efficient FFT processor for MIMO-OFDM based SDR systems

Cited by 3 publications

References 5 publications

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

An effective DC offset calibration method combined with analog and digital circuits for direct conversion receivers

High-Speed Continuous Wavelet Transform Processor for Vital Signal Measurement Using Frequency-Modulated Continuous Wave Radar

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