Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process

Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process

“…R on of each investigated circuit is relatively large in Figure 6 compared with other pure componentlevel orientated designs [2][3][4][5][6][7][8][9][10][11][12][13][14][15], confirming the validity of the utilized SB layout strategy for on-chip ESD elements burdening less system ESD current in PCB applications. Table 3 summarizes TLP test results in this sub-section.…”

“…A three-terminal test method presented in [12] is employed in this work to characterize turn-on behavior of the proposed circuit with respect to different transient pulses. In the three-terminal test method, the The concerned rise-times of applied pulses on V DD of TC include 5 ns and 100 µs in correspondence with the simulation stimuli in Figure 4.…”

“…Power-rail ESD clamp circuits are indispensable elements for the wholechip ESD protection strategy [2][3][4][5][6][7][8][9][10][11][12][13][14][15]. Transient-triggered power-rail ESD clamp circuits often utilize the resistor-capacitor (RC) network to distinguish ESD events from normal power-up pulses [2][3][4][5][6][7][8][9][10][11][12]. The fundamental design concern of transient-triggered circuits is to ensure the full active on state of the clamp device in ESD conditions while employing reduced RC time constants [2].…”

“…The fundamental design concern of transient-triggered circuits is to ensure the full active on state of the clamp device in ESD conditions while employing reduced RC time constants [2]. Feedback techniques, dual trigger paths and the capacitance-boosting technique provide efficient solutions towards the fundamental design concern [3][4][5][6][7][8][9][10][11][12]. However, transient-noise immunity remains an inevitable design challenge for transient-triggered circuits [3].…”

“…In the fast power-up simulation in Figure 4(a), V DD has a rise-time of 10 ns and peak voltage of 2.5 V. The peak gate voltage of M big in Figure 4(a) stays below its threshold voltage (around 0.6 V), indicating the falsetriggering immunity of the proposed circuit against this fast power-up pulse. For previously reported transient-triggered circuits in [2][3][4][5][6][7][8][9][10][11][12], the false-triggering immunity against fast power-up pulses with risetimes on the order of 100 ns has been extremely nice. In this work, it is shown that by utilizing the static ESD detection mechanism, the proposed circuit is immune to the fast power-up pulse with a rise-time as fast as that of an ESD event, achieving significant false-triggering immunity improvement relative to those of transient-triggered circuits.…”