Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process

Abstract

Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process SCIENCE CHINA Information Sciences 59, 042407 (2016); A novel ESD power supply clamp circuit with double pull-down paths SCIENCE CHINA Information Sciences 56, 102401 (2013); Dependency of well-contact density on MCUs in 65-nm bulk CMOS SRAM SCIENCE CHINA Information Sciences 62, 069402 (2019); Low leakage 3×VDD-tolerant ESD detection circuit without deep N-well in a standard 90-nm low-voltage CMOS process