Assembly issues in three flip chip processes

Zhong, Zhang

doi:10.1108/13565360010332390

Cited by 5 publications

(3 citation statements)

References 4 publications

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“…In these products, electronic packaging plays important roles such as supplying power to integrated circuit (IC) chips and distributing signals among microelectronic devices. As IC fabrication advances rapidly, electronic packaging faces more and more challenges [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Effects of Sintering Process Conditions on Size Shrinkages of Low-Temperature Co-Fired Ceramic Substrate

Zhong

Arulvanan

Ang

2006

Materials and Manufacturing Processes

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The effects of sintering process conditions on the size shrinkages of low-temperature co-fired ceramic (LTCC) substrate were investigated. The process variables investigated were thickness of the stacked raw tapes, lamination pressure, lamination-pressure holding time, pre-heating time, debinding time, sintering dwell time, and sintering temperature ramp. Results revealed that the size shrinkage percentage of the LTCC samples in the lateral directions was always smaller than that in the thickness direction. The lateral shrinkage deviations were less than 2.1% for all the experiments conducted in this study. Pre-heating time, lamination-pressure holding time, debinding time, sintering dwell time and sintering temperature ramp had almost no effects on the lateral size shrinkage of the LTCC samples, and the average of the lateral shrinkage values was 15.3%, with a standard deviation of 0.17%. Lamination pressure and stacked raw-tape thickness had effects on the lateral size shrinkage of the LTCC samples, and empirical equations for calculation of the size shrinkage values were obtained by curve fitting.

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Section: Introductionmentioning

confidence: 99%

Effects of Sintering Process Conditions on Size Shrinkages of Low-Temperature Co-Fired Ceramic Substrate

Zhong

Arulvanan

Ang

2006

Materials and Manufacturing Processes

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“…The adhesion of the encapsulant to the chip and the board coating are essential to the reliability of the package. In addition to the metallurgical interconnections provided by the solder joint, encapsulation provides additional adhesion strength to maintain the interconnection between the chip and the substrate (Zhong, 2000).…”

Section: Introductionmentioning

confidence: 99%

The reliability assessment of flip chip components

Huang

2004

Microelectronics International

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Flip chip technology involves the attachment of active side of the silicon chip onto printed circuit board or substrate. The interconnections are provided by solder bumps, which are arranged in the area under the chip. Encapsulation helps reduce the impact of the thermal stress that results from the mismatch in the coefficient of thermal expansion between the silicon chip and the substrate. The adhesion of the encapsulant to the chip and the board coating are essential to the reliability of the package. This paper studies the adhesion characteristics of an encapsulant to a flip chip package. The quality of the encapsulation was inspected using a scanning acoustic microscope. The electrical continuity of the assemblies was tested during the liquid‐to‐liquid thermal shock testing. The various delamination mechanisms were then studied. Delamination was found predominantly at the interface between the passivation layer and the encapsulant material. Comparisons were made between samples assembled by different materials used, such as chip passivation layer, encapsulant materials, and fluxes. Finally, the best material combination was determined.

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“…In the past decade, there has been rapid research and development for the manufacturing of advanced electronics packages (Zhong, 1999(Zhong, , 2000(Zhong, , 2001a. Package visual inspection (PVI) is the final visual inspection of electronics packages.…”

Section: Introductionmentioning

confidence: 99%

Inspection of electronics packages using the efficient perception technique

Zhong

Yue²

2004

Microelectronics International

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When engineers choose and arrange proper lighting sources for an inspection system, many of them rely on their own experience or guesswork without any guidance of theories. This paper discusses the efficient perception technique, i.e. the Torrance‐Sparrow model and its application to the selection and configuration of light emitting diode (LED) lighting sources for a package visual inspection system. Inspection of several typical package samples has been evaluated. The image changes of the sample packages are explained using the Torrance‐Sparrow model. The experimental results with the actual gray level values of the images are compared.

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Assembly issues in three flip chip processes

Cited by 5 publications

References 4 publications

Effects of Sintering Process Conditions on Size Shrinkages of Low-Temperature Co-Fired Ceramic Substrate

Effects of Sintering Process Conditions on Size Shrinkages of Low-Temperature Co-Fired Ceramic Substrate

The reliability assessment of flip chip components

Inspection of electronics packages using the efficient perception technique

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