Assertion-Based Design

Foster, Harry; Krolnik, Adam; Lacey, D.

doi:10.1007/b117047

Cited by 66 publications

(68 citation statements)

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“…1 The metric is computed for the circuit C, the environment constraints E, the property set P and the set of signals S. For each signal s from S its resulting coverage is determined and added up. The coverage for s is calculated on the basis of safe coverage, unsafe coverage, and unsafe weight.…”

Section: B Coverage Metricmentioning

confidence: 99%

“…the coverage of a signal s directly or indirectly depends on a signal t which again 1 Note that in cov(. .…”

Section: B Coverage Metricmentioning

confidence: 99%

“…Simulation-based validation of assertions, model checking and clever combinations from both worlds are available today (see e.g. [1], [2], [3], [4]). In addition, methods to estimate the verification quality have been proposed.…”

Section: Introductionmentioning

confidence: 99%

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A guiding coverage metric for formal verification

Haedicke¹,

Grosse²,

Drechsler³

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Considerable effort is made to verify the correct functional behavior of circuits and systems. To guarantee the overall success metric-driven verification flows have been developed. In these flows coverage metrics are omnipresent. Well established coverage metrics for simulation-based verification approaches exist. This is however not the case for formal verification where property checking is a major technique to prove the correctness of the implementation.In this paper we present a guiding coverage metric for this formal verification setting. Our metric reports a single number describing how much of the circuit behavior is uniquely determined by the properties. In addition, the coverage metric guides the verification engineer to achieve completeness by providing helpful information about missing scenarios. This information comes from a new behavior classification algorithm which determines uncovered behavior classes for a signal and allows to compute the coverage of a signal. To measure the complete circuit behavior we devise a coverage metric for a set of signals. The metric is calculated by partitioning the coverage computation into a safe part and an unsafe part where the latter one is weighted accordingly using recursion. This procedure takes into account that in practice properties refer to internal signals which in turn need to be covered them-self. Overall, our metric allows to track the verification progress in property checking and significantly aid the verification engineers in completing the property set.

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Section: B Coverage Metricmentioning

confidence: 99%

“…the coverage of a signal s directly or indirectly depends on a signal t which again 1 Note that in cov(. .…”

Section: B Coverage Metricmentioning

confidence: 99%

See 1 more Smart Citation

A guiding coverage metric for formal verification

Haedicke¹,

Grosse²,

Drechsler³

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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show abstract

“…This is a widely accepted problem in the integrated circuits industry and academic community, with numerous paper published in this subject Devadas and Keutzer, 1991;Fujiwara, 1990;Fujiwara, 1985;Chen and Breuer, 1985. Recent improvements of synthesis techniques allowed RTL-based designs to be adopted as the main design capture methodology used by designers. Moreover, the use of RTL-based designs enabled more aggressive validation techniques based on White-box verification as opposed to Black-box verification Foster et al, 2004. Black-box verification relates to the approach of providing stimulus to the input pins of a design and checking the results in its output pins. This approach offers very poor observability and controllability since a failure inside the design has to propagate to the output pins to be observable.…”

Section: Controllability and Observabilitymentioning

confidence: 99%

On-Chip Property Verification Using Assertion Processors

Nacif

Coelho

Foster

et al. 2006

IFIP International Federation for Information Processing

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White-box verification is a technique that reduces observability problems by locating a failure during design simulation without the need to propagate the failure to the I/O pins. White-box verification in chip level designs can be implemented using assertion checkers to ensure the correct behavior of a design. With chip gate counts growing exponentially, today's verification techniques, such as white-box, can not always ensure a bug free design. This paper proposes an assertion processor to be used with synthesized assertion checkers in released products to enable intelligent debugging of deployed designs. Extending whitebox verification techniques to deployed products helps locate errors that were not found during simulation / emulation phases. We present results of the insertion of assertion checkers and an assertion processor in an 8-Bit processor and a communication core.

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“…Property and equivalence checkers [3], [4], assertion-based verification and functional coverage tools [5], and recent advances in powerful solving engines such as Binary Decision Diagrams (BDD), Boolean satisfiability (SAT), and Satisfiability Modulo Theories (SMT) [6]- [8] have allowed verification Computer Aided Design (CAD) tools [9]- [12] to achieve great strides into their ability to aid engineers in detecting functional design errors. Despite these developments, there has been relatively less work directed towards debugging the error once it has been detected.…”

mentioning

confidence: 99%

Bounded Model Debugging

Keng

Safarpour

Veneris

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical design blocks exceeding half a million synthesized logic gates and error traces in the thousands of clock cycles, the complexity of the debugging problem poses a great challenge to automated debugging techniques. This work aims to address this daunting challenge by introducing the Bounded Model Debugging methodology that iteratively analyzes bounded sequences of the error trace. Two techniques are introduced in this methodology to solve this growing problem. The first technique iteratively analyzes bounded subsequences of the error trace of increasing size until the error is found or the entire trace is analyzed. The second technique partitions the error trace into non-overlapping bounded sequences of clock cycles which are each separately analyzed. A discussion of these two techniques is presented and a unified methodology that leverages the strengths of both techniques is developed. Empirical results on real industrial designs show that for large designs and long error traces the proposed methodology can find the actual error in 79% of cases with the first technique and 100% of cases with the second technique. In cases where the methodology is not used only 21% of cases are able to find the actual error. These numbers confirm the benefits of the proposed methodology to allow conventional automated debuggers to handle much larger real-life circuits.

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Assertion-Based Design

Cited by 66 publications

References 0 publications

A guiding coverage metric for formal verification

A guiding coverage metric for formal verification

On-Chip Property Verification Using Assertion Processors

Bounded Model Debugging

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