Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm

Jain, Tripti; Ramakrishna, Mukund; Gratz, Paul V.; Sprintson, Alex; Choi, Gwan

doi:10.1109/tcad.2011.2161190

Cited by 15 publications

(5 citation statements)

References 25 publications

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“…Jain et al [9] propose a multi-synchronous NoC (each router operating at the IP frequency), which avoids the synchronization overhead at the intermediate nodes via an Asynchronous Bypass Channel (ABC) around these nodes. Limitations of this approach include: (i) when a packet needs to make a direction turn (e.g., east to north), it must be latched, increasing the overall latency; (ii) since there is no connection establishment (our approach), routers employ bi-synchronous FIFOs to store packets in the event of congestion, also increasing the transmission latency.…”

Section: Related Workmentioning

confidence: 99%

Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication

Weber

Oliveira

Carara

et al. 2020

2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI)

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Systems-on-Chip (SoCs) with a large number of cores adopt Networks-on-chip (NoCs) as the communication infrastructure due to its scalability. The complexity to distribute a skew-free synchronous clock signal over the entire chip increases in current fabrication technologies due to the process variability. Thus, designers may choose among fully asynchronous and Globally Asynchronous, Locally Synchronous (GALS) NoCs. This work proposes an intermediate solution. Each Intellectual Property (IP) core may have its clock domain, and the NoC supports both synchronous and asynchronous communication. The NoC has its own clock domain, with the synchronous communication used to establish end-to-end paths. Once the end-to-end path is established, the NoC connects the IPs asynchronously, as wires with repeaters. The message is transmitted using handshake protocol at the source IP frequency. The benefit of the proposal is the reduction in the communication energy consumption (up to 52%). The cost is a latency increase (16% to 30%) and area overhead (4%).

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Section: Related Workmentioning

confidence: 99%

Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication

Weber

Oliveira

Carara

et al. 2020

2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI)

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show abstract

“…Moreover, there have been several input-buffered router proposals, which target mainly network latency, making single-cycle routers feasible, such as speculative allocation [29][30][31]. Recently proposed architectures such as the concentrated mesh (CMESH) [33], the express virtual channel (EVC) [35], Asynchronous Bypass Channels (ABC) [36], Distributed Shared-Buffer Routers (DBSBR) [37] and the flattened butterfly (FBFLY) [34] bypass intermediate routers in order to provide good performance and attempt to achieve an ideal latency i.e. the wire delay from the source to its destination.…”

Section: Related Workmentioning

confidence: 99%

Realization of Efficient High Throughput Buffering Policies for Network on Chip Router

Nazir¹,

Mir²

2016

IJCNIS

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Abstract-The communication between processing elements is suffering challenges due to power, area and latency. Temporary flit storage during communication consumes the maximum power of the whole power consumption of the chip. The majority of current NoCs consume a high amount of power and area for router buffers only. Removing buffers and virtual channels (VCs) significantly simplifies router design and reduces the power dissipation by a considerable amount. The buffering scheme used in virtual channeling in a networkon-chip based router plays a significant role in determining the performance of the whole network-onchip based mesh. Elastic buffer (EB) flow control is a simple control logic in the channels to use pipeline flipflops (FFs) as storage locations. With the use of elastic buffers, input buffers are no longer required hence leading to a simplified router design. In this paper properties of buffers are studied with a test microarchitecture router for several packet injection rates given at an input port. The prime contribution of this article is the evaluation of various forms of the elastic buffers for throughput, FPGA resource utilization, average power consumed, and the maximum speed offered. The article also gives a comparison with some available buffering policies against throughput. The paper presents the synthesis and implementation on FPGA platforms. The work will help NoC designers in suitable simple router implementation for their FPGA design. The implementation targets Virtex5 FPGA and Stratix III device family.

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“…Similar properties exist today on a single die due to increasing wire delays and transistor counts. Thus source synchronous signaling is relevant for today's systemon-chip and network-on-chip designs [7], [8], [9].…”

Section: Background a Related Workmentioning

confidence: 99%

SAS: Source Asynchronous Signaling Protocol for Asynchronous Handshake Communication Free from Wire Delay Overhead

Das

Vij

Stevens

2013

2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems

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Abstract-Asynchronous handshake protocol communication is accomplished by sending data down a communication link coupled with data validity information. Flow control is established by acknowledging the receipt of data, thereby enabling transmission of new data down the link. Handshake protocols operate at target cycle times based on system operational requirements. When the communication delay down wires increases beyond a certain point, the latency in sending the request and acknowledge signals across the link becomes longer than the target cycle time. This reduces the communication bandwidth below the desired value. This deleterious effect is particularly conspicuous on long links and network-on-chip communication. A method of enabling full communication bandwidth on wires with arbitrary delay when employing handshake communication is provided. This method supports end-to-end communication across links with arbitrarily large but finite latency without limiting the bandwidth, so long as line variation can be reliably controlled. This paper introduces the new SAS protocol, provides an efficient implementation, and reports the resultant significant energy and bandwidth improvements over conventional handshaking methods.

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Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm

Cited by 15 publications

References 25 publications

Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication

Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication

Realization of Efficient High Throughput Buffering Policies for Network on Chip Router

SAS: Source Asynchronous Signaling Protocol for Asynchronous Handshake Communication Free from Wire Delay Overhead

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