Atomic-layer-deposited silicon-nitride/SiO2 stacked gate dielectrics for highly reliable p-metal–oxide–semiconductor field-effect transistors

Abstract

An extremely thin (∼0.4 nm) silicon-nitride layer has been deposited on thermally grown SiO2 by an atomic-layer-deposition (ALD) technique. The boron penetration through the stacked gate dielectrics has dramatically been suppressed, and the reliability has been significantly improved, as confirmed by capacitance–voltage, gate-current–gate-voltage, and time-dependent dielectricbreakdown characteristics. The ALD technique allows us to fabricate an extremely thin, very uniform silicon-nitride layer with atomic-scale control.

Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics

“…Note that the maximum degradation of saturation drain current was around 2.5% at -V in both dielectrics. Considering the suppression of boron penetration [9]- [11], [13], better TDDB characteristics [9]- [13], and soft breakdown free phenomena [11]- [13] for the stack dielectrics, it is believed that the ALD Si-nitride/SiO stack dielectrics are a very promising candidate to replace the conventional SiO dielectrics for sub-100-nm technology application. However, for sub-60-nm technology application where the required EOT value becomes bellow 1.5 nm, additional scattering such as remote scattering caused by dipole charges existing at the ALD Si-nitride/SiO interface or the interface trapped charge may lower the carrier mobility for the stack dielectrics.…”

“…Recently, we have applied the self-limiting atomic-layer deposition (ALD) of Si nitride to the formation of Si-nitride/SiO stack gate dielectrics [9], [10], which shows more effective suppression of boron penetration than thermally grown SiO with identical thickness and the superior aspects of reliability issues such as hard breakdown field distribution, TDDB characteristics, soft breakdown (SBD) free phenomena [11]- [13]. However, an evaluation of the carrier mobility of the MOSFET with the stack gate dielectrics is still missing in the literature.…”

“…After formation of LOCOS isolation, adjust implants were introduced using phosphorous at cm and 20 keV. A thin layer ( nm) of Si nitride was deposited on thermally grown ultrathin SiO using the ALD technique [9], [10] followed by annealing at 600 C for 60 min in NH ambient just after the ALD. After a 200-nm-thick poly-Si gate was formed, source, drain, and gate ion implantation (20 keV, BF ) was carried out at a dose of cm followed by an activation annealing at 850 C for 10 min in N ambient.…”

Characterization of atomic-layer-deposited silicon nitride/SiO2 stacked gate dielectrics for highly reliable p-metal-oxide-semiconductor field-effect transistors

“…[13][14][15] In this technique, the thickness of the silicon nitride is controlled by layer by layer mode. Recently, 16 we have applied this technique for the atomprofile engineering of nitrogen in the gate insulator and have reported the preliminary results of the electrical characteristics of MOS diodes with a very thin ALD silicon nitride layer on top of the gate SiO 2 . In this article, we report in detail on the microstructure and electrical characteristics of the stacked gate dielectrics.…”

Soft breakdown free atomic-layer-deposited silicon-nitride/SiO/sub 2/ stack gate dielectrics

“…Also, oxynitride cannot eIiminate the boron penetration into the insulator layer, which causes the reliability degradation (2). Therefore, it is desirable to introduce the silicon nitride layer only at the poly-SVinsulator interface and stack gate dielectrics of silicon-nitride/SiO, have been suggested recently (3,4). We have developed and preliminary reported a new technique employing self-limiting atomic-layer deposition (ALD) of silicon nitride for the 2 1.5 P) C x 1.0 E 0.5 1 F i y r c I Thickncss of thc ALD silicon nitridc on SiO, mcasurcd by cllipsomchy vcrsus numbcr of dcposition cyclc.…”