Automatic layout synthesis for FIR filters using a silicon compiler

Abstract

A silicon compiler for FIR filters is presented. Unlike existing silicon compilers for designing Digital Signal Processor (DSP) chips, which need descriptions for signal processing algorithms as inputs, the synthesis system takes as inputs only filter specifications and processing word lengths, and generates the FIR filter mask pattems in a few minutes. The system consists of two programs: an FIR filter design program to determine FIR filter coefficients at the minimal filter order to meet design objectives and a module generator to generate mask pattems, according to optimal parameters obtained by the filter design program. For describing layout structures correctly and easily, the module generator provides graphical layout description tools and includes mechanisms to permit designing the structures before leaf-cells are completed. Layouts for several filters have been successfully generated in a short time. A single chip VLSI chrominance/luminance separator for NTSC composite TV signals employing four FIR filters generated by the system is shown.

Towards adaptive balanced computing (ABC) using reconfigurable functional caches (RFCs)

“…In other words, the original cache area is not included in the area overhead. The core area of design in [64] shown here is estimated in [62].…”

An efficient 2-D convolver chip for real-time image processing

“…Hence, the summation considering the weight k can be computed by shift-and-accumulation operations instead of multiplications. Several architectures based on the equation (2) have been proposed [5][6][7][8]. The direct implementation of the equation (2) requires nine 16-bit shift-and-accumulations (SAs) and the 16-bit tree adder (eight 16-bit adders).…”

“…Instead of a multiplier, one SA consisting of an accumulator and a 16-bit adder makes one product of F and H in eight cycles. Hence, the architectures based on the equation (2) [5][6][7][8] needs smaller VLSI area than the architectures based on the equation (1) [1]. To reduce the VLSI area further, this paper modifies the equation (2) to the equation (3) by exchanging summation sequence…”

“…The architecture can reduce the gate count by more than 70% of commercial filter chips having multipliers. In addition, compared with the previous architectures [5][6][7], the proposed filter architecture can reduce the size of the tree adder from 16-bit to 8-bit and the number of SAs from 9 to 1. The implemented filter chip can operates at 125 MHz and can process real-time image data.…”

“…Since multipliers occupy a large VLSI area [1,3,4], several convolution filter architectures based on the powers-of-two coefficients algorithm have been proposed [5][6][7][8][9]. For dedicated applications, convolution filter chips with hardwired shifters are particularly efficient [5][6][7].…”