Automatic synthesis of 3D asynchronous state machines

Yun, Yun; Dill,

doi:10.1109/iccad.1992.279310

Cited by 54 publications

(32 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore dynamic gates are most efficient when technology mapped from production rules [7] or other setreset synthesis methodology. Such an approach is employed by asynchronous synthesis CAD [2,16]. This is in stark contrast to the wasteful approach typically used in clocked designs where the precharge input is tied to the clock.…”

Section: Dynamic Gate Architecturesmentioning

confidence: 99%

Dynamic gates with hysteresis and configurable noise tolerance

Santhanam

Stevens

2007

2007 IFIP International Conference on Very Large Scale Integration

View full text Add to dashboard Cite

Dynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is presented. CDL replaces the standard keeper logic with a dual dynamic keeper gate that is applicable to all dynamic gate structures. CDL provides dynamic gates with two novel characteristics: hysteresis and arbitrarily configurable noise margins. However, these two benefits come at the cost of reducing the gain and increasing the energy of the dynamic gate. This paper compares the noise, energy, performance, gain, and total transistor width tradeoffs of CDL and three other logic families applied to a 65nm cell library consisting of 23 functions. The results show that the performance advantages of dynamic domino gates can be maintained while providing significantly enhanced noise margins using CDL structures.

show abstract

Section: Dynamic Gate Architecturesmentioning

confidence: 99%

Dynamic gates with hysteresis and configurable noise tolerance

Santhanam

Stevens

2007

2007 IFIP International Conference on Very Large Scale Integration

View full text Add to dashboard Cite

show abstract

“…As described by Yun, Nowick, and Dill [10,11], burst-mode circuits can also be implemented by using techniques similar to those of Huffman circuits. Since burst-mode circuits allow multiple input changes, one would expect to have the same hazard problems that motivated the single-input-change restriction in the Huffman circuits.…”

Section: Burst-mode Circuitsmentioning

confidence: 99%

“…A different design methodology, referred to as burst-mode, attempts to move even closer to synchronous design styles than the Huffman method. The burst-mode design style was developed by Nowick, Yun, and Dill [8][9][10][11] based on earlier work at HP laboratories by Davis, Stevens, and Coates [12]. As shown in Figure 5 (center), circuits are specified via a standard state-machine, where each arc is labeled by a non-empty set of inputs (an input burst), and a set of outputs (an output burst).…”

Section: Burst-mode Circuitsmentioning

confidence: 99%

Asynchronous design methodologies: an overview

1995

View full text Add to dashboard Cite

Asynchronous design has been an active area of research since at least the mid 1950's, but has yet to achieve widespread use. We examine the benefits and problems inherent in asynchronous computations, and in some of the more notable design methodologies. These include Huffman asynchronous circuits, burst-mode circuits, micropipelines, template-based and trace theory-based delay-insensitive circuits, signal transition graphs, change diagrams, and compilation-based quasidelay-insensitive circuits.

show abstract

“…The port controllers are implemented as asynchronous finite state machines using the extended burst mode paradigm of [19]. These are synthesised using the 3-D tool, which results in a synthesisable And -Or implementation [20].…”

Section: Gals Implementationsmentioning

confidence: 99%

Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

View full text Add to dashboard Cite

Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.

show abstract

Automatic synthesis of 3D asynchronous state machines

Cited by 54 publications

References 10 publications

Dynamic gates with hysteresis and configurable noise tolerance

Dynamic gates with hysteresis and configurable noise tolerance

Asynchronous design methodologies: an overview

Asynchronous on-chip networks

Contact Info

Product

Resources

About