Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline

Khayatzadeh, Mahmood; Lian, Yong

doi:10.1109/tvlsi.2013.2265265

Cited by 32 publications

(14 citation statements)

References 22 publications

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“…Complex mechanisms are used to reduce the abovementioned problem. One such method is to interleave the bits (Khayatzadeh and Lian 2014), which implies the logically adjacent bits of a single word will not be kept actually adjacent. Such a situation is depicted in Fig.…”

Section: Soft Error and The Half-select Issuementioning

confidence: 99%

Low-power half-select free single-ended 10 transistor SRAM cell

Sinha

Islam

2016

Microsyst Technol

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Section: Soft Error and The Half-select Issuementioning

confidence: 99%

Low-power half-select free single-ended 10 transistor SRAM cell

Sinha

Islam

2016

Microsyst Technol

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“…On the other hand, a disadvantage of the 10T SRAM is that it suffers from a large area overhead to accommodate the additional transistors in its architecture. To address this disadvantage, an average-8T SRAM architecture based on a 130-nm technology was proposed; this SRAM architecture is a good alternative to the previously proposed SRAMs in that it addresses the half-select issue with no write-back scheme, and it exhibits a competitive area [9]. However, a drawback of this 8T SRAM is that its read delay increases considerably when it is fabricated using a more advanced technology such as a 22-nm FinFET technology that involves a large variation in V th , because a tradeoff between the read stability and the read delay exists.…”

Section: Introductionmentioning

confidence: 99%

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

Kang

Jeong

Yang

et al. 2016

IEEE Trans. VLSI Syst.

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The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an average-8T SRAM architecture, a full-swing local bitline (BL) that is connected to the gate of the read buffer can be achieved with a boosted wordline (WL) voltage. However, in the case of an average-8T SRAM based on an advanced technology, such as a 22-nm FinFET technology, where the variation in threshold voltage is large, the boosted WL voltage cannot be used, because it degrades the read stability of the SRAM. Thus, a full-swing local BL cannot be achieved, and the gate of the read buffer cannot be driven by the full supply voltage (V DD ), resulting in a considerably large read delay. To overcome the above disadvantage, in this paper, a differential SRAM architecture with a full-swing local BL is proposed. In the proposed SRAM architecture, full swing of the local BL is ensured by the use of cross-coupled pMOSs, and the gate of the read buffer is driven by a full V DD , without the need for the boosted WL voltage. Various configurations of the proposed SRAM architecture, which stores multiple bits, are analyzed in terms of the minimum operating voltage and area per bit. The proposed SRAM that stores four bits in one block can achieve a minimum voltage of 0.42 V and a read delay that is 62.6 times lesser than that of the average-8T SRAM based on the 22-nm FinFET technology.Index Terms-Bit-interleaving, FinFET, low-voltage operation, static random access memory (SRAM). 1063-8210

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“…Various techniques have also been proposed to increase the write SNM of SRAM cells, but, as mentioned, the RSNM is predominantly the bottleneck when lowering V DD . Dynamically lowering the cell V DD during writes [22], floating the cell ground during writes [25], increasing the word-line voltage [12], and keeping a negative voltage on the bit-line [13] all improve the reliability when writing to the cell. These techniques all require additional circuitry, increase power consumption, and, in some cases, decrease the hold SNM of neighbouring cells.…”

Section: Low-power Srammentioning

confidence: 99%

“…Making access devices stronger is a more promising approach. Upsizing access transistors ( [30], [39]), and boosting the word-line voltage ( [25] [12]) are good ways to achieve this, but the effect of upsizing transistors is lessened in sub-threshold operation, and boosting voltage requires additional circuitry.…”

Section: Literature Reviewmentioning

confidence: 99%

“…While the previous two studies succeeded in adapting the 6T SRAM cell for subthreshold operation, they dramatically increased area consumption. The design proposed in [12] presents a sub-threshold differential SRAM architecture with a robust read scheme and minimum area. The SRAM architecture is illustrated in Figure 3 [12].…”

Section: Sram With Bit Interleaving and 1k Bits Per Bitlinementioning

confidence: 99%

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Power and Area Efficient Sub-threshold 6T SRAM with Horizontal Local Bit-Lines and Bit-Interleaving

Basuta¹

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SRAM in the typical microprocessor consumes a substantial amount of on-chip area and significantly contributes to static power dissipation. Previous studies have shown that sub-threshold operation presents a minimum energy point that is optimal if ultralow power consumption is desired. However, the standard 6T SRAM cell does not operate at sub-threshold voltages. Instead, designs with higher transistor counts are typically used for sub-threshold operation. These designs generally have low integration density.This study presents a new SRAM architecture with minimum area that utilizes a modified 6T SRAM cell for sub-and near-threshold operation in ultra-low power applications. This new architecture introduces horizontal bit-lines, mitigates halfselect disturb, and supports bit-interleaving. The proposed design's stability was thoroughly tested in the presence of process, temperature, and voltage variations, and compared to the standard 6T and traditional 8T cells. A 32kb SRAM block implementing the proposed architecture was designed, simulated, and contrasted to a traditional 8T SRAM cell block.The simulated 32kb SRAM block operates at a maximum frequency of 544.8 khz and 6.70 Mhz for the read and write operations, respectively, and consumes 0.586 pJ/bit in the read operation and 0.17 pJ/bit in the write operation. A very similar 32kb SRAM block consisting of the traditional 8T SRAM cell was found to have a maximum frequency of 544.8 kHz and 2.89 Mhz for the read and write operations, respectively, and consumes 0.736 pJ/bit in the read operation and 0.205 pJ/bit in the write operation. The results show that the proposed design has lower power consumption than the 8T SRAM block, comparable read performance, and better write performance. This was all achieved while only having a 10% increase in area per bit over the conventional 6T thin-cell layout.ii

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Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline

Cited by 32 publications

References 22 publications

Low-power half-select free single-ended 10 transistor SRAM cell

Low-power half-select free single-ended 10 transistor SRAM cell

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

Power and Area Efficient Sub-threshold 6T SRAM with Horizontal Local Bit-Lines and Bit-Interleaving

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