Band-like transport in high mobility unencapsulated single-layer MoS2 transistors

Jariwala, Deep; Sangwan, Vinod K.; Late, Dattatray J.; Johns, James E.; Dravid, Vinayak P.; Marks, Tobin J.; Lauhon, Lincoln J.; Hersam, Mark C.

doi:10.1063/1.4803920

Cited by 382 publications

(402 citation statements)

References 44 publications

Supporting

Mentioning

367

Contrasting

Order By: Relevance

“…15 Comparison of previous reports on hysteresis in MoS 2 devices with this work is listed in Table 1. Hysteresis observed in previous studies [16][17][18] has been attributed to several possibilities such as adsorption of water molecules, [18][19][20][21] oxide traps close to MoS 2 , 22 oxide-MoS 2 interface traps 23,24 and gate voltage stress effects. 25 A lack of uniformity in the hysteresis data and consensus on its origin among the reports listed in Table 1 results, at least partly, from differences in measurement conditions as well as device architecture.…”

Section: Introductionmentioning

confidence: 91%

Reversible hysteresis inversion in MoS2 field effect transistors

et al. 2017

View full text Add to dashboard Cite

The origin of threshold voltage instability with gate voltage in MoS 2 transistors is poorly understood but critical for device reliability and performance. Reversibility of the temperature dependence of hysteresis and its inversion with temperature in MoS 2 transistors has not been demonstrated. In this work, we delineate two independent mechanisms responsible for thermally assisted hysteresis inversion in gate transfer characteristics of contact resistance-independent multilayer MoS 2 transistors. Variable temperature hysteresis measurements were performed on gated four-terminal van der Pauw and two-terminal devices of MoS 2 on SiO 2 . Additional hysteresis measurements on suspended (~100 nm air gap between MoS 2 and SiO 2 ) transistors and under different ambient conditions (vacuum/nitrogen) were used to further isolate the mechanisms. Clockwise hysteresis at room temperature (300 K) that decreases with increasing temperature is shown to result from intrinsic defects/traps in MoS 2 . At higher temperatures a second, independent mechanism of charge trapping and de-trapping between the oxide and p + Si gate leads to hysteresis collapse at~350 K and anti-clockwise hysteresis (inversion) for temperatures >350 K. The intrinsic-oxide trap model has been corroborated through device simulations. Further, pulsed current-voltage (I-V) measurements were carried out to extract the trap time constants at different temperatures. Non-volatile memory and temperature sensor applications exploiting temperature dependent hysteresis inversion and its reversibility in MoS 2 transistors have also been demonstrated. npj 2D Materials and Applications (2017) 1:34 ; doi:10.1038/s41699-017-0038-y INTRODUCTION Among two-dimensional materials, graphene 1,2 was the first to be isolated and studied with respect to electronic applications. Due to lack of an energy bandgap in graphene, other 2D materials such as layered transition metal dichalcogenides (TMDs) comprising a wide selection of materials with different bandstructures, and therefore different electrical and optical properties, have garnered significant attention.3-5 Molybdenum disulfide (MoS 2 ) has emerged as a prospective candidate for transistor applications. The presence of a direct bandgap (~1.8 eV) in monolayer form and an indirect bandgap (~1.2 eV) in multilayer MoS 2 makes it a promising channel material for field effect transistors (FETs).

show abstract

Section: Introductionmentioning

confidence: 91%

Reversible hysteresis inversion in MoS2 field effect transistors

et al. 2017

View full text Add to dashboard Cite

show abstract

“…In this report, we demonstrate the fabrication and operation of a gate-tunable p-n heterojunction diode using semiconducting single-walled carbon nanotubes (s-SWCNTs) (p-type) (20) and single layer (SL)-MoS 2 (n-type) (21,22). Fig.…”

mentioning

confidence: 99%

Gate-tunable carbon nanotube–MoS ₂ heterojunction p-n diode

Jariwala

Sangwan

et al. 2013

Proc. Natl. Acad. Sci. U.S.A.

Self Cite

387

343

View full text Add to dashboard Cite

The p-n junction diode and field-effect transistor are the two most ubiquitous building blocks of modern electronics and optoelectronics. In recent years, the emergence of reduced dimensionality materials has suggested that these components can be scaled down to atomic thicknesses. Although high-performance fieldeffect devices have been achieved from monolayered materials and their heterostructures, a p-n heterojunction diode derived from ultrathin materials is notably absent and constrains the fabrication of complex electronic and optoelectronic circuits. Here we demonstrate a gate-tunable p-n heterojunction diode using semiconducting single-walled carbon nanotubes (SWCNTs) and single-layer molybdenum disulfide as p-type and n-type semiconductors, respectively. The vertical stacking of these two direct band gap semiconductors forms a heterojunction with electrical characteristics that can be tuned with an applied gate bias to achieve a wide range of charge transport behavior ranging from insulating to rectifying with forward-to-reverse bias current ratios exceeding 10 4 . This heterojunction diode also responds strongly to optical irradiation with an external quantum efficiency of 25% and fast photoresponse <15 μs. Because SWCNTs have a diverse range of electrical properties as a function of chirality and an increasing number of atomically thin 2D nanomaterials are being isolated, the gate-tunable p-n heterojunction concept presented here should be widely generalizable to realize diverse ultrathin, highperformance electronics and optoelectronics.2D transition metal dichalcogenide | single layer MoS 2 | van der Waals heterostructure | rectifier | photodetector

show abstract

“…In particular, we focus on the anisotropy of the mobility and its temperature dependence which in monolayer MoS 2 FETs has been shown to be caused by the temperature variability of the charge screening [13] and is sometimes attributed to the inelastic phonon scattering of electrons. [16,17] Given that encapsulation with a high-κ oxide insulator has been used to enhance carrier mobility in ultrathin 2D crystals, [17] we also model its effects on charge transport.We state the main assumptions of our charge transport model. As in monolayer graphene and TMD crystals, we suppose that charge transport in the metallic phase [17] in monolayer phosphorene is dominated by charged impurity (CI) scattering at low and room temperature.…”

mentioning

confidence: 99%

Anisotropic charged impurity-limited carrier mobility in monolayer phosphorene

Ong

Zhang

2014

Journal of Applied Physics

View full text Add to dashboard Cite

The room temperature carrier mobility in atomically thin 2D materials is usually far below the intrinsic limit imposed by phonon scattering as a result of scattering by remote charged impurities in its environment. We simulate the charged impurity-limited carrier mobility µ in bare and encapsulated monolayer phosphorene. We find a significant temperature dependence in the carrier mobilities (µ ∝ T −γ ) that results from the temperature variability of the charge screening and varies with the crystal orientation. The anisotropy in the effective mass leads to an anisotropic carrier mobility, with the mobility in the armchair direction about one order of magnitude larger than in the zigzag direction. In particular, this mobility anisotropy is enhanced at low temperatures and high carrier densities. Under encapsulation with a high-κ overlayer, the mobility increases by up to an order of magnitude although its temperature dependence and its anisotropy are reduced.The search for alternatives to graphene for nanoelectronic applications has expanded lately to include transition metal dichalcogenides (TMDs) [1][2][3][4] and other atomically thin two-dimensional (2D) crystals. [5,6] Phosphorene, an ultrathin form of black phosphorus (BP), has recently garnered considerable interest because of its potentially high carrier mobility (∼ 300 cm 2 V −1 s −1 in few-layer samples [7]), direct band gap [8] and electrical conductance anisotropy. [9] In contrast, measurements of unprocessed monolayer TMD crystals have yielded room-temperature mobilities typically below 10 cm 2 V −1 s −1 [10] although the mobility in similarly thick multilayer MoS 2 has been measured to be around 200 cm 2 V −1 s −1 .[11] However, recent experimental studies of the hole mobility in few-layer BP suggest that thinning phosphorene leads to a substantial reduction in the mobility, [8,12] possibly due to the closer proximity between the charge carriers and remote Coulomb impurities in the substrate. Extrapolating to a single phosphorene layer, the carrier mobility would ultimately be limited by charged impurity scattering even at room temperature, as in monolayer MoS 2 . [13] Despite intense theoretical interest in monolayer phosphorene, [14,15] there has not been a successful demonstration of a working monolayer phosphorene-based field-effect transistor (FET) to date.[8] Nonetheless, the eventual realization of such a device is highly probable in our opinion since monolayer phosphorene has been physically isolated [8]. The atomic thinness of a monolayer 2D crystal also allows for higher on-off current ratios, providing superior electrostatic modulation of the channel carrier density via an external gate. In a FET, this results in small off-currents and large switching ratios which are advantageous for low-power device applications. Thus, it would be advantageous to have a model of charge transport in supported monolayer phosphorene that takes into account its anisotropic character and can be used to interpret electrical transport data from realistic phosph...

show abstract

Band-like transport in high mobility unencapsulated single-layer MoS2 transistors

Cited by 382 publications

References 44 publications

Reversible hysteresis inversion in MoS2 field effect transistors

Reversible hysteresis inversion in MoS2 field effect transistors

Gate-tunable carbon nanotube–MoS ₂ heterojunction p-n diode

Anisotropic charged impurity-limited carrier mobility in monolayer phosphorene

Contact Info

Product

Resources

About

Band-like transport in high mobility unencapsulated single-layer MoS2 transistors

Cited by 382 publications

References 44 publications

Reversible hysteresis inversion in MoS2 field effect transistors

Reversible hysteresis inversion in MoS2 field effect transistors

Gate-tunable carbon nanotube–MoS 2 heterojunction p-n diode

Anisotropic charged impurity-limited carrier mobility in monolayer phosphorene

Contact Info

Product

Resources

About

Gate-tunable carbon nanotube–MoS ₂ heterojunction p-n diode