Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints

Lakshmikanthan, Preetham; Govindarajan, Sriram; Srinivasan, V.; Vemuri, Ranga

doi:10.1007/3-540-45591-4_127

Cited by 3 publications

(1 citation statement)

References 8 publications

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“…As designs become large and complex, it is necessary to perform parallel design by the temporal partitioning or architectural synthesis [2][3][4][5][6][7]. The temporal partitioning divides the target application into a number of specification segments that are destined to be executed one by one in the target reconfigurable hardware device [1].…”

Section: Introductionmentioning

confidence: 99%

A framework of architectural synthesis for dynamically reconfigurable FPGAs

Liu

Tanougast

Weber

2008

2008 IEEE International SOC Conference

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Reconfiguration latency is an important factor which impacts the system performance in the reconfigurable computing design. In this paper, a framework is proposed that presents a novel approach for an optimal implementation of algorithms on FPGA based reconfigurable system. The method optimizes the temporal partitioning by performing a similar-rate-computing-based architectural synthesis. It gives the possibility to merge the related partitions during the implementation of a target architecture by the architectural synthesis based on reusing of the common task. Our approach proposes a final solution based on the computation of the mutual similar rate (M.S.R.) for a RTR implementation with a synthesis option. The proposed approach attempts to reduce the number of the temporal partitions for minimizing the overall execution time. An example is presented to illustrate this novel approach. With the architectural synthesis, the number of partition was decreased. The results demonstrate that are capable and efficient for an optimized implementation in the reconfigurable design.

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Section: Introductionmentioning

confidence: 99%

A framework of architectural synthesis for dynamically reconfigurable FPGAs

Liu

Tanougast

Weber

2008

2008 IEEE International SOC Conference

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A Reliability-Aware Partitioner for Multi-FPGA Platforms

Bolchini

Sandionigi

2011

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism

Hara

Tomiyama

Honda

et al. 2010

IEICE Trans. Fundamentals

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A novel method to efficiently synthesize hardware from a large behavioral description in behavioral synthesis is proposed. For a program with functions executable in parallel, this proposed method determines a behavioral partitioning which simultaneously minimizes the overall datapath area and the complexity of the controller while maximizing performance of a synthesized circuit by fully exploiting function-level parallelism of a behavioral description. This method is formulated as an integer programming problem. Experimental results demonstrate that this method leads to a shift of the explorable design space so that superior solutions which could not be explored by earlier work are included, showing the effectiveness of our proposed method.

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Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints

Abstract: Abstract

Cited by 3 publications

References 8 publications

A framework of architectural synthesis for dynamically reconfigurable FPGAs

A framework of architectural synthesis for dynamically reconfigurable FPGAs

A Reliability-Aware Partitioner for Multi-FPGA Platforms

Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism

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