Benchmarking of 3-D MOSFET Architectures: Focus on the Impact of Surface Roughness and Self-Heating

Abstract

Tremendous improvements in the fabrication technology has allowed us to scale the physical dimensions of the transistors and also to develop different promising 3D architectures that may allow us to continue the Moore's law. In this work we perform a comparative delay analysis of different architectures and study the impact of surface roughness and self-heating on oncurrent using a comprehensive in-house simulation framework comprising of Schrödinger, Poisson and Boltzmann transport equations solvers along with relevant scattering mechanisms and self-heating. Our results highlight that the parasitic capacitance can alter the relative ranking of the architectures from delay point of view. We demonstrate that the surface roughness can cause architecture and material dependent degradation and hence it is necessary to account for it in simulations benchmarking different architectures.

Photoresponsive characteristics of EFG-grown iron-doped (100) Ga2O3 substrate with low dark current

“…Based on equation (1)-( 4), the l R , D* and LDR of the fabricated Fe-doped β-Ga 2 O 3 solar-blind UV photodetector are calculated to be 0.145 mA cm −2 , 6 ´10 10 cm Hz 1/2 W −1 (Jones) and 75.56 dB at 5 V under 254 nm UV light radiation with intensity of 750 μW cm −2 , respectively. However, the materials-dependent current may well be degraded due to the large RMS of 5.49 nm for the Fe-doped Ga 2 O 3 substrate [25], translating to the relatively low I photo and l R . Overall, the results suggest that the incident photons could be efficiently photo generated to create photo-generated electron-hole pairs, contributing to the I photo .…”

Modeling Nanoscale III–V Channel MOSFETs with the Self-Consistent Multi-Valley/Multi-Subband Monte Carlo Approach

“…TCAD can handle more complicated 3D devices such as trigate FinFETs, gate-all-around MOSFETs, and stacked nanowires that are candidates for aggressively scaled technology nodes. The TCAD calibration procedure provided here vs. 2D MV-MSMC can be applied to these structures as well, although verification against 3D full-quantum approaches and solutions of the BTE for the 1D carrier gas [20,27,51] may be needed.…”

Study of gate current in advanced MOS architectures

“…To this end, several innovative device architectures like the double gate, FinFET, stacked nanosheets, have been implemented or are under investigation. These architec-tures have been extensively analyzed and optimized from the point of view of improving the electrostatic integrity and the on-state performance, and reducing the variability [1], [2]. [3], [4].…”