Beyond silicon: Strained-SiGe channel FinFETs

Nanda, Rajib Kumar; Dash, T. P.; Das, Sanghamitra; Maiti, C. K.

doi:10.1109/mami.2015.7456578

Cited by 4 publications

(5 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A few atomic planes at the bottom are frozen in their perfect lattice positions. The cavity contains the Si 1 − x Ge x alloy with a total volume of 843 nm 3 . The rest of the box is filled by Si atoms.…”

Section: Set Upmentioning

confidence: 99%

“…However, the limit of scaling is being approached for conventional planar transistors and new issues have arisen as a result of this aggressive scaling, such as the short channel effect (SCE) or the reduction of threshold voltage [1]. This approach to miniaturization impacts also 3 Author to whom any correspondence should be addressed.…”

Section: Introductionmentioning

confidence: 99%

“…The cross section is also illustrated. [3]. Consequently, the implementation of strain techniques developed for planar transistors is crucial to improve the transistor performance.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Strain compensation by relieving defects in SiGe channel for FinFET technologies

Prieto-Depedro

Martín-Bragado

2020

Semicond. Sci. Technol.

View full text Add to dashboard Cite

Current generations of FinFET devices are incorporating SiGe alloys as stressor material in channel regions in order to enhance hole mobility, drive current and channel conductivity. However, the presence of SiGe gives rise to new issues to be controlled during the device fabrication process, such as the strain retention or defectivity control, as they may seriously impact the quality of the strained SiGe channel and so the final device performance. The present work addresses the study of defect formation during the optimized integration of SiGe FinFETs for 10 nm technology nodes, aimed at determining the Ge threshold content for the nucleation of defects. Due to the relevance of atomistic models in determining the mechanisms and nature of defect formation, molecular dynamics (MD) simulations have been performed to emulate the FinFET fabrication process. The channel region is generated by removing a portion of the total volume of the Si substrate, further refilled with Si 1 − x Ge x alloy to form the co-integrated FinFETs. After deposition, the presence of Ge induces a lattice distortion which is expected to be relieved by defect formation. Samples are annealed varying the Ge fraction, allowing to determine that threshold Ge content for the nucleation of defects is x = 0.27. MD provides also the nature of the formed defects, which have been suggested to be twinning developed at {111} planes and 60• misfit dislocations. Simulation results have been compared to experimental observations, both in good agreement.

show abstract

Section: Set Upmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Strain compensation by relieving defects in SiGe channel for FinFET technologies

Prieto-Depedro

Martín-Bragado

2020

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…It allows level set surface descriptions, as well as explicit surfaces to be used. Nanda et al [83] were able to simulate the fabrication of strained FinFETs using this framework. Victory Cell [84] is a related tool, which uses cell based and explicit surface representations in order to improve the description of ion implantation and diffusion.…”

Section: Simulation Softwarementioning

confidence: 99%

Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review

2018

View full text Add to dashboard Cite

Semiconductor device dimensions have been decreasing steadily over the past several decades, generating the need to overcome fundamental limitations of both the materials they are made of and the fabrication techniques used to build them. Modern metal gates are no longer a simple polysilicon layer, but rather consist of a stack of several different materials, often requiring multiple processing steps each, to obtain the characteristics needed for stable operation. In order to better understand the underlying mechanics and predict the potential of new methods and materials, technology computer aided design has become increasingly important. This review will discuss the fundamental methods, used to describe expected topology changes, and their respective benefits and limitations. In particular, common techniques used for effective modeling of the transport of molecular entities using numerical particle ray tracing in the feature scale region will be reviewed, taking into account the limitations they impose on chemical modeling. The modeling of surface chemistries and recent advances therein, which have enabled the identification of dominant etch mechanisms and the development of sophisticated chemical models, is further presented. Finally, recent advances in the modeling of gate stack pattering using advanced geometries in the feature scale are discussed, taking note of the underlying methods and their limitations, which still need to be overcome and are actively investigated.

show abstract

“…Stress and strain engineering have so far been used in Si CMOS technology as a technology booster to enhance the carriers transport via band structure modulation (Maiti, 2017;Nanda et al, 2015]. Since 22 nm technology nodes, the scaling of metal-oxidesemiconductor field effect transistors (MOSFETs) alone is not sufficient to enhance the performance of integrated circuits (Kuhn, 2012).…”

Section: Introductionmentioning

confidence: 99%

Role of stress/strain mapping and random dopant fluctuation in advanced CMOS process technology nodes

Dash¹,

Jena²,

Mohapatra³

et al. 2020

IJNBM

View full text Add to dashboard Cite

In this work, biaxial and uniaxial strain techniques are implemented in the channel for both p-and n-type FinFETs necessary for advanced CMOS applications. Stress/strain mapping in strained-Si (n-type) and strained-SiGe (p-type) channels (in trapezoidal tri-gate FinFET devices) are studied through three-dimensional (3D) numerical simulation, with particular focus on the enhancement of drain current. Following the strain/stress profiles simulated, the piezoresistive changes are implemented in the simulator to describe the strain effects on device operation. Further, we have investigated the impacts of random discrete dopant variability on the characteristics of a 14-nm gate length FinFET transistors (both n and p-type) using a 3D finite element quantum corrected drift-diffusion device simulator. We have also found the fluctuation of critical device parameters such as threshold voltage (VTH), sub-threshold slope (SS), on current (ION), and off state current (IOFF), etc., mainly originated from the randomness of distribution of the dopants.

show abstract

Beyond silicon: Strained-SiGe channel FinFETs

Cited by 4 publications

References 5 publications

Strain compensation by relieving defects in SiGe channel for FinFET technologies

Strain compensation by relieving defects in SiGe channel for FinFET technologies

Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review

Role of stress/strain mapping and random dopant fluctuation in advanced CMOS process technology nodes

Contact Info

Product

Resources

About