Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter

Abstract

Publication information IEEE Transactions on Circuits and SystemsAbstract-Bang-bang phase-locked loops (BBPLLs) are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In the presence of jitter, the nonlinear loop is typically analyzed by linearizing the BPD and applying linear transfer functions in the analysis. In contrast to a linear PD, the linearized gain of a BPD depends on the rms jitter and the type of jitter (either non-accumulative or accumulative). Previous works considered the case of nonaccumulative reference clock jitter and showed that the BPD gain is inversely proportional to the rms jitter when the latter is small or large. In this brief we consider the case of accumulative DCO jitter and derive an asymptotic closed-form expression for the BPD gain which becomes exact in the limit of small and large jitter. Contrary to the reference clock jitter case, the BPD gain is constant for small DCO jitter and is inversely proportional to the square of jitter for large DCO jitter; in the latter case, the timing jitter has a normal-Laplace distribution.Index Terms-Bang-bang phase-locked loop, timing jitter, binary phase detector gain, asymptotic analysis.

Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

“…For large input jitter, the output jitter of a second-order loop is higher than that of a first-order loop, and is inversely proportional to the square root of the stability factor. Simple addition of the small-jitter formula (20) and the large-jitter formula (24) gives a good prediction of the total output jitter.…”

“…Since > by assumption A1, it follows from (20) that a second-order loop has a lower output jitter for small than a first-order loop. For the loop design, since typically ≫ , the second term in (20) can be neglected and out,so ≈ out,fo to a good approximation.…”

“…Having obtained expressions for the small and large-jitter regime, the total output jitter out,so can be approximately predicted by simple addition of the expressions (20) and (24). Figure 5 plots out,so as a function of , the parameter being the stability factor = / (see also [1, Fig.…”

“…The effect of jitter can be accurately analyzed using Markov models [12], but their applicability has been limited to first-order loops to date [13]- [16]. It is more common to linearize the BPD nonlinearity and apply linear transfer functions in the analysis [13], [17]- [20]. The loop linearization for the case of nonaccumulative reference clock jitter (due to white phase noise) has been developed in [13] and applied to the analysis of a secondorder loop in [18].…”

Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs

“…In spite of mathematical difficulties in the analysis of nonlinear iterative maps relevant for electronics and phase locked loops, there is a certain class of maps whose properties are studied quite well -Σ∆ modulators. This type of nonlinear map originated from Analogue-to-Digital converters [16], [26], [27] and find themselves in Bang-Bang All-Digital Phase-Locked Loops (BBADPLL) [12]- [14], [28]. For example, statistical properties of oversampled Σ∆ modulators were studied by Gray in [26].…”