Bit line sensing strategy for testing for dataretention faults in CMOS SRAMs

IET Comput. Digit. Tech.

Ivanov

et al. 2007

The test scheduling problem for built-in self-tested embedded SRAMs (e-SRAMs) when data retention faults (DRFs) are considered is addressed here. We proposed a 'retention-aware' test power model by taking advantage of the fact that there is near-zero test power during the pause time for testing DRFs. The proposed test scheduling algorithm then utilises this new test power model to minimise the total testing time of e-SRAMs while not violating given power constraints, by scheduling some e-SRAM tests during the pause time of DRF tests. Without losing generality, we consider both cases where the pause time for DRFs is fixed and cases where it can be varied. Experimental results show that the proposed 'retention-aware' test power model and the corresponding test scheduling algorithm can reduce the testing time of e-SRAMs significantly with negligible computational time.

Section: Because Of This Fixed Wait Period Whenever An 'A' Type Of Mmentioning

confidence: 99%

Test scheduling for built-in self-tested embedded SRAMs with data retention faults

IET Comput. Digit. Tech.

Ivanov

et al. 2007

“…Though this model is simple, it is overly pessimistic in regards to e-SRAMs testing where Data Retention Faults (DRFs) are included as target faults. Even though Design-for-Test (DFT) techniques exist for DRFs [11][12][13][14][15], they often come with high hardware/performance overhead and design efforts. As a result, the most common practice for DRF test today is still to use two separate delay cycles in a test, during which the memories under test conduct no operation and thus consumes "zero" or negligible power [16][17].…”

Section: Introductionmentioning

confidence: 99%

A retention-aware test power model for embedded SRAM

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

Yang

et al. 2005

This paper addresses the test power model problem for embeddedSRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a "single-rectangle" power model to describe their test power consumption. This leads to significant waste of test time since e-SRAM test usually includes a long period of "zero" power consumption for the detection of Data Retention Faults. This paper takes advantage of this "zero" power period and proposes a "retention-aware" test power model for e-SRAMs. The proposed model is evaluated and its impact on test time reduction is reported for various scenarios in terms of retention test duration, memory capacities, test algorithm complexities, etc. A formula is derived to predict the maximum test time reduction when the "zero" power period is fully utilized in a SoC environment.

“…Like the methodology in [18] and [19], in NWRTM, a special write cycle is created to distinguish a good cell from a faulty cell when subjected to a DRF caused by an open defect on the pull-up PMOS. A typical 6T SRAM cell with storage node A and complementary storage node B, shown in Figure 6, is used to illustrate the differences between the specifically designed "No Write Recovery Cycle (NWRC)" and a normal write cycle.…”

Section: Designs For Testing Data Retention Faultsmentioning

confidence: 99%

“…In the test algorithms from [18] and [19], by setting the bitlines BL and BLb to a given voltage level between VCC and GND during the write operation, e.g., when the access NMOS is "on", a good cell fails to flip while a faulty cell does. Similarly, we set the voltage level of BL and BLb to "float" GND and "true" GND respectively.…”

Section: Figure 6 a Typical 6t Sram Cell And Its Precharge Control Cmentioning

confidence: 99%

Designs for reducing test time of distributed small embedded SRAMs

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.

Ivanov

This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (e-SRAMs). This architecture improves the one proposed in [4,5]. The improvements are mainly two-fold. On one hand, the testing of time-consuming Data Retention Faults (DRFs), that is neglected by the test architecture in [4,5], is now considered and performed via a DFT technique referred to as the "No Write Recovery Test Mode (NWRTM)". On the other hand, a parallel Local Response Analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs. Results from our evaluations show that the proposed test architecture can achieve a better defect coverage and test time compared to those obtained in [4,5], with a negligible area cost.