Bitline GND sensing technique for low-voltage operation FeRAM

Bitline-Capacitance-Insensitive Readout Circuit using Capacitive-Feedback Charge-Integration Scheme for Low-Voltage FeRAM

“…It should be noted that the power dissipation of the proposed circuit was evaluated by simulation and revealed to be almost the same as or less than the BGS [3] scheme under the same conditions where 0.35m CMOS technology, 3 V power supply and 55 ns access time were assumed.…”

“…"Bitline GND Sensing (BGS) Technique," where bitline voltage is kept constant at GND level and C BL -independent large readout voltage can be obtained by charge transfer mechanism of pMOS source follower, was proposed [3]. However, multiple voltage levels and complex timing control are required in this technique and therefore not suit to the small capacity memories utilized in smart card products.…”

Development of ferroelectric RAM (FRAM) for mass production

“…We have introduced a new concept of 16-bit word based reference cell array consisting of 17 transistors and 17 capacitors as shown in fig.7. Only 17 cells at intersection of word line (WL) and plate line (PL) are activated simultaneously using staircase word line [3]. 17 ferroelectric capacitors experience same polarization and thermal history.…”

“…In our development, an interface control between ferroelectric material and electrode is found to be crucial for decreasing the operation voltages with maintaining the large polarization. Circuit improvements of the sensing amplifier are also effective for obtaining robust reliability of the 4Mb or larger memory-size FRAM [2,3]. Our FRAM has evolved from 5-V operation 0.5m CMOS node to 1.8 V operation 0.18-m CMOS node.…”

Development of Ferroelectric RAM (FRAM) for Mass Production

“…In our development, an interface control between ferroelectric material and electrode is found to be crucial for decreasing the operation voltages with maintaining the large polarization. This capacitor fabrication improvement with circuit improvements of the sensing amplifier [6,7] has successfully realized robust reliability of the 4 Mb or larger memory-size FRAM. Our FRAM has evolved from 5 V operation and 0.5 μm node CMOS to 1.8 V operation and 0.18…”